IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERC" />
參數(shù)資料
型號(hào): IDT72V3632L10PQF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 17/29頁
文件大?。?/td> 0K
描述: IC BIFIFO 512X36X2 10NS 132-PQFP
標(biāo)準(zhǔn)包裝: 36
系列: 72V
功能: 異步,同步
存儲(chǔ)容量: 36.8K(512 x 36 x 2)
數(shù)據(jù)速率: 100MHz
訪問時(shí)間: 10ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 132-BQFP 緩沖式
供應(yīng)商設(shè)備封裝: 132-PQFP(24.13x24.13)
包裝: 托盤
其它名稱: 72V3632L10PQF
24
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
Figure 16. Timing for AEB
AEB
AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
Figure 15. FFB
FFB
FFB Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.
CSA
EFA
MBA
ENA
A0-A35
CLKA
FFB
CLKB
CSB
4660 drw 17
W/RB
12
B0-B35
MBB
ENB
tCLK
tCLKH
tCLKL
tENS2
tENH
tA
tSKEW1
tCLK
tCLKH
tCLKL
tENS2
tDS
tENH
tDH
To FIFO2
Previous Word in FIFO2 Output Register
Next Word From FIFO2
LOW
W/
RA LOW
LOW
HIGH
LOW
(1)
FIFO2 Full
tWFF
Write
AEB
CLKA
ENB
4660 drw 18
ENA
CLKB
2
1
tENS2
tENH
tSKEW2
tPAE
tENS2
tENH
X1 Words in FIFO1
(X1+1) Words in FIFO1
(1)
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