參數(shù)資料
型號: IDT72V36100L7.5PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: FIFO
英文描述: 3.3 VOLT HIGH-DENSITY SUPERSYNC II⑩ 36-BIT FIFO
中文描述: 64K X 36 OTHER FIFO, 5 ns, PQFP128
封裝: PLASTIC, TQFP-128
文件頁數(shù): 31/48頁
文件大小: 476K
代理商: IDT72V36100L7.5PF
37
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
NOTES:
1. n =
PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4.
PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
2. In FWFT mode: D = maximum FIFO depth. D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)
Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
WCLK
tENS
tENH
WEN
HF
tENS
tHF
RCLK
tHF
REN
6117 drw27
tCLKL
tCLKH
D/2 words in FIFO(1),
[
+ 1
] words in FIFO(2)
D-1
2
D/2 + 1 words in FIFO
(1),
[
+ 2
] words in FIFO(2)
D/2 words in FIFO(1),
[
+ 1
] words in FIFO(2)
D-1
2
D-1
2
WCLK
tCLKH
tCLKL
tENS
tENH
WEN
PAE
tENS
tPAEA
n + 1 words in FIFO(2),
n+2wordsinFIFO(3)
n words in FIFO(2),
n + 1 words in FIFO(3)
RCLK
tPAEA
REN
6117 drw26
n words in FIFO(2),
n + 1 words in FIFO(3)
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