參數(shù)資料
型號: IDT72V36100L7.5PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: FIFO
英文描述: 3.3 VOLT HIGH-DENSITY SUPERSYNC II⑩ 36-BIT FIFO
中文描述: 64K X 36 OTHER FIFO, 5 ns, PQFP128
封裝: PLASTIC, TQFP-128
文件頁數(shù): 25/48頁
文件大?。?/td> 476K
代理商: IDT72V36100L7.5PF
31
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
NOTES:
1. Retransmit setup is complete after
EF returns HIGH, only then can a read operation begin.
2.
OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore,
FF will be HIGH throughout the Retransmit setup procedure.
D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 11. Retransmit Timing (IDT Standard Mode)
tREF
tRTS
tENH
6117 drw16
tA
tENS
Wx
WCLK
RCLK
REN
RT
EF
PAF
HF
PAE
Q0 - Qn
tSKEW2
12
1
W1
tPAFS
tHF
tPAES
tREF
Wx+1
2
W2
tENH
WEN
tENS
tRTS
tENS
tENH
(3)
tA
(3)
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IDT72V36100L7-5PFI8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 64X36 7-5NS 128QFP