IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM <" />
參數(shù)資料
型號: IDT72V36100L7-5BBI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 7/48頁
文件大?。?/td> 0K
描述: IC FIFO 64X36 7-5NS 144BGA
標(biāo)準(zhǔn)包裝: 1
系列: 72V
功能: 同步
存儲容量: 2.3K(64 x 36)
數(shù)據(jù)速率: 166MHz
訪問時間: 5ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 144-BGA
供應(yīng)商設(shè)備封裝: 144-PBGA(13x13)
包裝: 托盤
其它名稱: 72V36100L7-5BBI
15
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
Figure 3. Programmable Flag Offset Programming Sequence
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
WCLK
RCLK
X
XX
X
XX
LD
0
X
1
0
WEN
0
1
0
X
1
REN
1
0
1
X
0
1
1X
SEN
1
X
0
No Operation
Write Memory
Read Memory
No Operation
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
IDT72V36100
IDT72V36110
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Serial shift into registers:
Ending with Full Offset (MSB)
32 bits for the 72V36100
34 bits for the 72V36110
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
6117 drw06
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