IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
參數(shù)資料
型號(hào)： IDT72V2113L6PF
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 15/46頁(yè)
文件大?。?/td> 0K
描述： IC FIFO SUPERSYNCII 6NS 80-TQFP
標(biāo)準(zhǔn)包裝： 45
系列： 72V
功能： 同步
存儲(chǔ)容量： 4.7Mb（262k x 18）
訪(fǎng)問(wèn)時(shí)間： 4ns
電源電壓： 3.15 V ~ 3.45 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-TQFP（14x14）
包裝： 托盤(pán)
其它名稱(chēng)： 72V2113L6PF
22
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
JUNE 1, 2010
If asynchronous
PAF configurationisselected,the PAF isassertedLOW
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK).
PAFisresettoHIGH
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK).Ifsynchronous
PAF
configuration is selected, the
PAFisupdatedontherisingedgeofWCLK.See
Figure 20 for Asynchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode).
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE)
The Programmable Almost-Empty flag (
PAE)willgoLOWwhentheFIFO
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in Table 2.
In FWFT mode, the
PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in Table 2.
See Figure 19, Synchronous Programmable Almost-Empty Flag Timing
(IDT Standard and FWFT Mode), for the relevant timing information.
If asynchronous
PAEconfigurationisselected,the PAEisassertedLOW
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK).
PAEisresettoHIGH
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK).Ifsynchronous
PAE
configuration is selected, the
PAEisupdatedontherisingedgeofRCLK.See
Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
HALF-FULL FLAG (
HF)
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO
beyondhalf-fullsets
HFLOW.TheflagremainsLOWuntilthedifferencebetween
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets
HF
HIGH.
InIDTStandardmode,ifnoreadsareperformedafterreset(
MRSorPRS),
HF will go LOW after (D/2 + 1) writes to the FIFO. If x18 Input or x18 Output
bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the
IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D =
262,144 for the IDT72V2103 and 524,288 for the IDT72V2113.
In FWFT mode, if no reads are performed after reset (
MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO. If x18 Input or x18 Output bus
Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the
IDT72V2113. If both x9 Input and x9 Output bus Widths are selected,
D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113.
See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Mode),
for the relevant timing information. Because
HFisupdatedbybothRCLKand
WCLK, it is considered asynchronous.
DATA OUTPUTS (Q0-Qn)
(Q0 - Q17) data outputs for 18-bit wide data or (Q0 - Q8) data outputs for 9-
bit wide data.
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