SUPERSYNC FIFOTM
參數(shù)資料
型號(hào): IDT72V2101L15PF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 26/27頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SS 131X18 15NS 64QFP
標(biāo)準(zhǔn)包裝: 45
系列: 72V
功能: 同步
存儲(chǔ)容量: 2.3K(131 x 18)
數(shù)據(jù)速率: 67MHz
訪問(wèn)時(shí)間: 15ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 托盤
其它名稱: 72V2101L15PF
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
Number of
Words in
FIFO
0
1 to n (1)
0
1 to n (1)
(n+1) to 131,072
131,073 to (262,144-(m+1))
(262,144-m) (2) to 262,143
262,144
TABLE II
STATUS FLAGS FOR FWFT MODE
IDT72V2101
IDT72V2111
FF
PAF HF
PAE EF
HH
HL
L
HH
HL
H
HH
H
HH
L
H
HL
L
H
LL
LH
H
TABLE I
STATUS FLAGS FOR IDT STANDARD MODE
4669 drw 05
0
1 to n+1(1)
0
1 to n+1(1)
(n+2) to 262,145
262,146 to (524,289-(m+1))
(524,289-m)
(2)
to 524,288
524,289
IR
PAF HF PAE OR
LH
H
L
H
LH
H
L
H
HHL
LH
L
H
L
LLL
H
L
HL
L
H
L
IDT72V2101
IDT72V2111
Number of
Words in
FIFO
(n+1) to 262,144
262,145 to (524,288-(m+1))
(524,288-m) (2) to 524,287
524,288
(n+2) to 131,073
131,074 to (262,145-(m+1))
(262,145-m)
(2)
to 262,144
262,145
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
PROGRAMMING FLAG OFFSETS
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72V2101/
72V2111hasinternalregistersfortheseoffsets.Defaultsettingsarestatedinthe
footnotesofTable1andTable2.OffsetvaluescanbeprogrammedintotheFIFO
inoneoftwoways;serialorparallelloadingmethod.Theselectionoftheloading
method is done using the
LD(Load)pin.DuringMasterReset,thestateofthe
LD input determines whether serial or parallel flag offset programming is
enabled. A HIGH on
LD during Master Reset selects serial loading of offset
valuesandinaddition,setsadefault
PAEoffsetvalueof3FFH(athreshold1,023
words from the empty boundary), and a default
PAF offset value of 3FFH (a
threshold 1,023 words from the full boundary). A LOW on
LD during Master
Resetselectsparallelloadingofoffsetvalues,andinaddition,setsadefault
PAE
offset value of 07FH (a threshold 127 words from the empty boundary), and
a default
PAF offset value of 07FH (a threshold 127 words from the full
boundary). See Figure 3, Offset Register Location and Default Values.
In addition to loading offset values into the FIFO, it also possible to read the
current offset values. It is only possible to read offset values via parallel read.
Figure 4, Programmable Flag Offset Programming Sequence, summa-
rizes the control pins and sequence for both serial and parallel programming
modes. For a more detailed description, see discussion that follows.
The offset registers may be programmed (and reprogrammed) any time
after Master Reset, regardless of whether serial or parallel programming
has been selected.
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