參數(shù)資料
型號: IDT72T7295L4-4BBG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 53/53頁
文件大?。?/td> 0K
描述: IC FIFO 32768X72 4-4NS 324-BGA
標準包裝: 1
系列: 72T
訪問時間: 3.2ns
電源電壓: 2.375 V ~ 2.625 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 324-BGA
供應商設備封裝: 324-PBGA(19x19)
包裝: 托盤
其它名稱: 72T7295L4-4BBG
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
Symbol
Rating
Commercial
Unit
VTERM
TerminalVoltage
–0.5 to +3.6(2)
V
with respect to GND
TSTG
StorageTemperature
–55 to +125
°C
IOUT
DC Output Current
–50 to +50
mA
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.125V, TA = 0
°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
2.375
2.5
2.625
V
GND
Supply Voltage
0
V
VIH
Input High Voltage
LVTTL
1.7
3.45
V
eHSTL
VREF+0.2
VDDQ+0.3
V
HSTL
VREF+0.2
VDDQ+0.3
V
VIL
Input Low Voltage
LVTTL
-0.3
0.7
V
eHSTL
-0.3
VREF-0.2
V
HSTL
-0.3
VREF-0.2
V
VREF(1)
VoltageReferenceInput
eHSTL
0.8
0.9
1.0
V
HSTL
0.68
0.75
0.9
V
TA
OperatingTemperatureCommercial
0
70
°C
TA
OperatingTemperatureIndustrial
-40
85
°C
Symbol
Parameter
Min.
Max.
Unit
ILI
InputLeakageCurrent
–10
10
μA
ILO
OutputLeakageCurrent
–10
10
μA
VOH(5)
Output Logic “1” Voltage,
IOH = –8 mA @VDDQ = 2.5V
± 0.125V (LVTTL)
VDDQ -0.4
V
IOH = –8 mA @VDDQ = 1.8V
± 0.1V (eHSTL)
VDDQ -0.4
V
IOH = –8 mA @VDDQ = 1.5V
± 0.1V (HSTL)
VDDQ -0.4
V
VOL
Output Logic “0” Voltage,
IOL = 8 mA
@VDDQ = 2.5V
± 0.125V (LVTTL)
0.4V
V
IOL = 8 mA
@VDDQ = 1.8V
± 0.1V (eHSTL)
0.4V
V
IOL = 8 mA
@VDDQ = 1.5V
± 0.1V (HSTL)
0.4V
V
ICC1(1,2)
Active VCC Current (VCC = 2.5V)
I/O = LVTTL
80
mA
I/O = HSTL
130
mA
I/O = eHSTL
130
mA
ICC2(1)
Standby VCC Current (VCC = 2.5V)
I/O = LVTTL
20
mA
I/O = HSTL
90
mA
I/O = eHSTL
90
mA
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Compliant with JEDEC JESD8-5. VCC terminal only.
NOTE:
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
2. Outputs are not 3.3V tolerant.
Symbol
Parameter(1)
Conditions
Max.
Unit
CIN(2,3)
Input
VIN = 0V
10(3)
pF
Capacitance
COUT(1,2)
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz.
WCS = HIGH, REN or RCS = HIGH.
2. Typical ICC1 calculation:
for LVTTL I/O ICC1 (mA) = 2.24mA x fs, fs = WCLK frequency = RCLK frequency (in MHz)
for HSTL or eHSTL I/O ICC1 (mA) = 55mA + (2.24mA x fs), fs = WCLK frequency = RCLK frequency (in MHz)
3. Typical IDDQ calculation: With Data Outputs in High-Impedance: IDDQ (mA) = 0.15mA x fs
With Data Outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x N)/2000
fs = WCLK frequency = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, N = Number of outputs switching.
tA = 25
°C, CL = capacitive load (pf).
4. Total Power consumed: PT = (VCC x ICC) + VDDQ x IDDQ).
5. Outputs are not 3.3V tolerant.
CAPACITANCE (TA= +25
°C, f = 1.0MHz)
NOTES:
1. With output deselected, (
OE
≥ VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
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