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參數(shù)資料
| 型號(hào)： | IDT72T72105L4-4BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 25/53頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO 65536X72 4-4NS 324-BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 72T |
| 訪問時(shí)間： | 3.2ns |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-BGA |
| 供應(yīng)商設(shè)備封裝： | 324-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T72105L4-4BB |
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31
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
THE INSTRUCTION REGISTER
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
The Instruction is used to select the test to be performed, or the test data
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
at the completion of the shifting process when the TAP controller is at Update-
IRstate.
The instruction register must contain 4 bit instruction register-based cells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serial outputs they are the least significant bits.
TEST DATA REGISTER
The Test Data register contains three test data registers: the Bypass, the
Boundary Scan register and Device ID register.
These registers are connected in parallel between a common serial input
and a common serial data output.
The following sections provide a brief description of each element. For a
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEE Std. 1149.1-1990).
TEST BYPASS REGISTER
The register is used to allow test data to flow through the device from TDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
When the bypass register is selected by an instruction, the shift register stage
is set to a logic zero on the rising edge of TCLK when the TAP controller is in
the Capture-DR state.
The operation of the bypass register should not have any effect on the
operation of the device in response to the BYPASS instruction.
THE BOUNDARY-SCAN REGISTER
The Boundary Scan Register allows serial data TDI be loaded in to or read
out of the processor input/output ports. The Boundary Scan Register is a part
of the IEEE 1149.1-1990 Standard JTAG Implementation.
THE DEVICE IDENTIFICATION REGISTER
The Device Identification Register is a Read Only 32-bit register used to
specify the manufacturer, part number and version of the processor to be
determined through the TAP in response to the IDCODE instruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is dropped in the 11-bit Manufacturer ID field.
For the IDT72T7285/72T7295/72T72105/72T72115, the Part Number
field contains the following values:
IDT72T7285/95/105/115 JTAG Device Identification Register
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits)
Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
JTAG INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
when the TAP controller is in the Shift-IR state. The instruction is decoded to
perform the following:
Select test data registers that may operate while the instruction is current.
Theothertestdataregistersshouldnotinterferewithchipoperationandthe
selected data register.
Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16 different possible instructions. Instructions are decoded as follows.
Hex Value Instruction
Function
0x00
EXTEST
Select Boundary Scan Register
0x02
IDCODE
Select Chip Identification data register
0x01
SAMPLE/PRELOAD Select Boundary Scan Register
0x03
HIGH-IMPEDANCE
JTAG
0x0F
BYPASS
Select Bypass Register
JTAG Instruction Register Decoding
The following sections provide a brief description of each instruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEE Std. 1149.1-1990).
EXTEST
The required EXTEST instruction places the IC into an external boundary-
testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI
and TDO. During this instruction, the boundary-scan register is accessed to
drive test data off-chip via the boundary outputs and receive test data off-chip
via the boundary inputs. As such, the EXTEST instruction is the workhorse of
IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts
and of logic cluster function.
IDCODE
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDIandTDO.Thedeviceidentificationregisterisa32-bitshiftregistercontaining
information regarding the IC manufacturer, device type, and version code.
Accessingthedeviceidentificationregisterdoesnotinterferewiththeoperation
oftheIC.Also,accesstothedeviceidentificationregistershouldbeimmediately
available, via a TAP data-scan operation, after power-up of the IC or after the
TAP has been reset using the optional
TRSTpinorbyotherwisemovingtothe
Test-Logic-Resetstate.
SAMPLE/PRELOAD
The required SAMPLE/PRELOAD instruction allows the IC to remain in a
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
between TDI and TDO. During this instruction, the boundary-scan register can
be accessed via a date scan operation, to take a sample of the functional data
enteringandleavingtheIC.Thisinstructionisalsousedtopreloadtestdatainto
the boundary-scan register before loading an EXTEST instruction.
HIGH-IMPEDANCE
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state
as well as three-state types) of an IC to a disabled (high-impedance) state and
selects the one-bit bypass register to be connected between TDI and TDO.
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI
to TDO without affecting the condition of the IC outputs.
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
functionalmodeandselectstheone-bitbypassregistertobeconnectedbetween
TDI and TDO. The BYPASS instruction allows serial data to be transferred
through the IC from TDI to TDO without affecting the operation of the IC.
Device
Part# Field
IDT72T7285
0493
IDT72T7295
0492
IDT72T72105
0491
IDT72T72115
0490
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T72105L4-4BBG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 65536X72 4-4NS 324BGA |
| IDT72T72105L5BB | 功能描述:IC FIFO 65536X72 5NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T72105L5BBGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 65536X72 4-4NS 324BGA |
| IDT72T72105L6-7BB | 功能描述:IC FIFO 65536X72 6-7NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T72115L10BB | 功能描述:IC FIFO 131072X72 10NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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