IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO
參數(shù)資料
型號: IDT72T1895L4-4BB
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 29/55頁
文件大?。?/td> 0K
描述: IC FIFO 65536X18 4NS 144BGA
標準包裝: 1
系列: 72T
功能: 異步,雙端口
存儲容量: 1.1M(65K x 18)
數(shù)據(jù)速率: 10MHz
訪問時間: 3.4ns
電源電壓: 2.375 V ~ 2.625 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 144-BGA
供應商設備封裝: 144-PBGA(13x13)
包裝: 托盤
其它名稱: 72T1895L4-4BB
35
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
Figure 10. Partial Reset Timing
tRS
PRS
tRSR
REN
tRSS
5909 drw14
tRSR
WEN
RT
SEN
tRSF
OE = HIGH
OE = LOW
PAE
PAF, HF
Q0 - Qn
tRSF
EF/OR
FF/IR
tRSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
tRSS
NOTE:
1. During Partial Reset the High-Impedance control of the Qn data outputs is provided by
OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset
is complete.
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