參數(shù)資料
型號(hào)： IDT7290820PQF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 路由/交換
英文描述： TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
中文描述： TELECOM, DIGITAL TIME SWITCH, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù)： 12/27頁(yè)
文件大小： 174K
代理商： IDT7290820PQF
12
COMMERCIAL TEMPERATURE RANGE
IDT7290820 5V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
'
"
&
,.,"
DR1
0
0
1
1
DR0
0
1
0
1
Data Rate Selected
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Reserved
Master Clock Required
4.096 MHz
8.192 MHz
16.384 MHz
Reserved
Read/Write Address:
Reset Value:
01
H
,
0000
H
.
Bit
15-10
9-5
Name
Description
Unused
BPD4-0
(Block Programmng Data)
Must be zero for normal operation.
These bits carry the value to be loaded into the connection memory block whenever the memory block
programmng feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is
set to 1, the contents of the bits BPD4-0 are loaded into bit 15 and 11 of the connection memory. Bit 10 to
bit 0 of the connection memory are set to 0.
A zero to one transition of this bit enables the memory block programmng function. The BPE and
BPD4-0 bits in the IMS register have to be defined in the same write operation. Once the BPE bit is set
HIGH, the device requires two frames to complete the block programmng. After the programmng function
has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE
or MBP can be set to 0 to ensure proper operation. When BPE = 1, the other bit in the IMS register
must not be changed for two frames to ensure proper operation.
When ODE = 0 and OSB = 0, the output drivers of TX0 to TX15 are in high impedance mode. When
ODE= 0 and OSB = 1, the output driver of TX0 to TX15 function normally. When ODE = 1, TX0 to TX15
output drivers function normally.
A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR
register changes fromzero to one, the evaluation procedure stops. To start another fame evaluation
cycle, set this bit to zero for at least one frame.
Input/Output data rate selection. See Table 9 for detailed programmng.
4
BPE
(Begin Block Programmng
Enable)
3
OSB
(Output Stand By)
2
SFE
(Start Frame Evaluation)
1-0
DR0-1
(Data Rate Select)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
BPD4 BPD3 BPD2 BPD1 BPD0
BPE
OSB
SFE
DR1
DR0
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