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參數(shù)資料
| 型號： | IDT7290820PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 路由/交換 |
| 英文描述： | TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, TQFP-100 |
| 文件頁數(shù)： | 4/27頁 |
| 文件大小： | 174K |
| 代理商： | IDT7290820PF |
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COMMERCIAL TEMPERATURE RANGE
IDT7290820 5V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
SYMBOL
GND
Vcc
TX0-15
(1)
NAME
I/O
DESCRIPTION
Ground.
Vcc
TX Output 0 to 15
(Three-state Outputs)
RX Input 0 to 15
Ground Rail.
+5.0 Volt Power Supply.
Serial data output stream These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon
the value programmed at bits DR0-1 in the IMS register.
Serial data input stream These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon
the value programmed at bits DR0-1 in the IMS register.
When the WFPS pin is LOW, this input accepts and automatically identifies frame synchronization signals formatted
according to ST-BUS
and GCI specifications. When the WFPS pin is HIGH, this pin accepts a negative frame
pulse which conforms to WFPS formats.
When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK
(4.096 MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode.
Serial clock for shifting data in/out on the serial streams (RX/TX 0-15). Depending upon the value programmed
at bits DR0-1 in the IMS register, this input accepts a 4.096, 8.192 or 16.384 MHz clock.
JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pull-
up when not driven.
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when
JTAG scan is not enabled.
Provides the clock to the JTAG test logic. This pin is pulled high by an internal pull-up when not driven.
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled
by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure
that the IDT7290820 is in the normal functional mode.
Connect to GND for normal operation. This pin must be LOW for the IDT7290820 to function normally and to
comply with IEEE 1114 (JTAG) boundary scan requirements.
This input (active LOW) puts the IDT7290820 in its reset state that clears the device internal counters, registers
and brings TX0-15 and mcroport data outputs to a high-impedance state. The time constant for a power up
reset circuit must be a mnimumof five times the rise time of the power supply. In normal operation, the
RESET
pin must be held LOW for a mnimumof 100ns to reset the device.
When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in
ST-BUS
/GCI mode.
When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal
memories.
For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with
CS
to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This
active LOW input works in conjunction with
CS
to enable the read and write operations. For Intel multiplexed bus
operation, this input is
RD
. This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs.
In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/
W
. This input controls
the direction of the data bus lines (AD0-7, D8-15) during a mcroprocessor access. For Intel multiplexed bus
operation, this input is
WR
. This active LOW input is used with
RD
to control the data bus (AD0-7) lines as inputs.
Active LOW input used by a mcroprocessor to activate the mcroprocessor port of IDT7290820.
This input is used if multiplexed bus operation is selected via the IMinput pin. For Motorola non-multiplexed
bus operation, connect this pin to ground. This pin is pulled low by an internal pull-down when not driven.
When IMis HIGH, the mcroprocessor port is in the multiplexed mode. When IMis LOW, the mcroprocessor
port is in non-multiplexed mode. This pin is pulled low by an internal pull-down when not driven.
These pins are the eight least significant data bits of the mcroprocessor port. In multiplexed mode, these pins
are also the input address bits of the mcroprocessor port.
O
RX0-15
(1)
I
F0i
(1)
Frame Pulse
I
FE/HCLK
(1)
Frame Evaluation/
HCLK Clock
CLK
(1)
Clock
I
I
TMS
Test Mode Select
I
TDI
Test Serial Data In
I
TDO
Test Serial Data Out
O
TCK
(1)
TRST
Test Clock
Test Reset
I
I
IC
(1)
Internal Connection
I
RESET
(1)
Device Reset
(Schmtt Trigger Input)
I
WFPS
(1)
Wide Frame
Pulse Select
Address 0-7
I
A0-7
(1)
I
DS/
RD
(1)
Data Strobe/Read
I
R/
W
/
WR
(1)
Read/Write / Write
I
CS
(1)
AS/ALE
(1)
Chip Select
Address Strobe or
Latch Enable
CPU Interface Mode
I
I
IM
(1)
I
AD0-7
(1)
Address/Data Bus 0 to 7 I/O
NOTE:
1. These pins are 5V tolerant.
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