參數(shù)資料
型號(hào): IDT728981
廠商: Integrated Device Technology, Inc.
英文描述: TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128
中文描述: 時(shí)隙交換數(shù)字開(kāi)關(guān)128 × 128
文件頁(yè)數(shù): 5/10頁(yè)
文件大?。?/td> 91K
代理商: IDT728981
5
C
ommercial Temperature Range
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
Table 4. Connection Memory High Register
Table 5. Connection Memory Low Register
Table 3. Control Register Configuration
Bit
7
Name
Description
SM(Split Memory)
When 1, all subsequent reads are fromthe Data Memory and writes are to the Connection Memory LOW, except
when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for the
operations. In either case, the StreamAddress Bits select the subsection of the memory which is made available.
When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when the ODE
pin is LOW. When 0, the Connection Memory bits for each channel determne what is output.
unused
0-0 - Not to be used.
0-1 - Data Memory (read only fromthe mcroprocessor port)
1-0 - Connection Memory LOW
1-1 - Connection Memory is HIGH
unused
The number expressed in binary notation on these bits refers to the input or output streamwhich corresponds to the
subsection of memory made accessible for subsequent operations.
6
PE (Processor Mode)
5
4-3
MS1-MS0
(Memory Select Bits)
2
1-0
STA1-0
(StreamAddress Bits)
7
6
5
4
3
2
1
0
Mode Control
Bits
Memory Select
Bits
Stream Address
Bits
(unused)
(unused)
Bit
2
Name
Description
CS (Channel Source)
When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel
and stream When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the
Data Memory and determne the source of the connection to the location's channel and stream
unused
If the ODE pin is HIGH and bit 6 of the Control Register is 0, then this bit enables the output driver for the location's
channel and stream This allows individuals channels on individuals streams to be made high-impedance, allowing
switching matrices to be constructed. A 1 enables the driver and a 0 disables it.
1
0
OE (Output Enable)
7
6
5
4
3
2
1
0
No Corresponding Memory
- These bits give 0s if read
CS
(unused)
OE
Bit
7
6-5
(1)
Name
Description
unused
The number expressed in binary notation on these 2 bits are the number of the streamfor the source of the connection.
Bit 6 is the most significant bit, e.g., If bit 6 is 1, bit 5 is 0 then the source of the connection is a channel on RX2.
The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the
connection (the streamwhere the channel lies is defined by bits 7, 6 and 5). Bit 4 is the most significant bit, e.g., if bit 4
is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.
StreamAddress Bits
4-0
(1)
Channel Address Bits
7
6
5
4
3
2
1
0
Stream Address
Bits
(unused)
Channel Address Bits
NOTE:
1.If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and streamassociated with
this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and streamassociated with this location.
相關(guān)PDF資料
PDF描述
IDT728981DB TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128
IDT728981J TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128
IDT728981P TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128
IDT728985 TIME SLOT INTERCHANGE DIGITAL SWITCH
IDT7290820 TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
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