參數(shù)資料
型號(hào): IDT7284L20PAI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: FIFO
英文描述: 4K X 9 BI-DIRECTIONAL FIFO, 20 ns, PDSO56
封裝: TSSOP-56
文件頁(yè)數(shù): 6/11頁(yè)
文件大?。?/td> 143K
代理商: IDT7284L20PAI
4
IDT
IDT7280/81/82
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 – D8)
Data inputs for 9-bit wide data.
CONTROLS:
RESET (
RS
RS)
Reset is accomplished whenever the Reset (
RS) input is taken to a LOW
state. During reset, both internal read and write pointers are set to the first
location. A reset is required after power up before a write operation can take
place. Both the Read Enable (
R
R) and Write Enable (W
W
W) inputs must be
in the HIGH state during the window shown in Figure 2, (i.e., tRSS
before the rising edge of
RS
RS) and should not change until tRSR after
the rising edge of
RS
RS. Half-Full Flag (HF
HF
HF) will be reset to HIGH after
Reset (
RS
RS).
WRITE ENABLE (
W
W)
A write cycle is initiated on the falling edge of this input if the Full Flag
(
FF) is not set. Data set-up and hold times must be adhered to with respect
to the rising edge of the Write Enable (
W). Data is stored in the RAM array
sequentially and independently of any on-going read operation.
After half of the memory is filled and at the falling edge of the next write
operation,theHalf-FullFlag(
HF)willbesettoLOWandwillremainsetuntilthe
difference between the write pointer and read pointer is less than or equal to
one half of the total memory of the device. The Half-Full Flag (
HF)isthenreset
by the rising edge of the read operation.
To prevent data overflow, the Full Flag (
FF)willgoLOW,inhibitingfurther
write operations. Upon the completion of a valid read operation, the Full Flag
(
FF) will go HIGH after tRFF, allowing a valid write to begin. When the FIFO
is full, the internal write pointer is blocked from
W, so external changes in
W will not affect the FIFO when it is full.
READ ENABLE (
R
R)
A read cycle is initiated on the falling edge of the Read Enable (
R)
provided the Empty Flag (
EF)isnotset.ThedataisaccessedonaFirst-In/First-
Out basis, independent of any ongoing write operations. After Read Enable (
R)
goes HIGH, the Data Outputs (Q0– Q8) will return to a high impedance condition
until the next Read operation. When all data has been read from the FIFO, the
Empty Flag (
EF)willgoLOW,allowingthe“final”readcyclebutinhibitingfurther
read operations with the data outputs remaining in a high impedance state.
Once a valid write operation has been accomplished, the Empty Flag (
EF) will
go HIGH after tWEF and a valid Read can then begin. When the FIFO is empty,
the internal read pointer is blocked from
RsoexternalchangesinRwillnotaffect
the FIFO when it is empty.
FIRST LOAD/RETRANSMIT (
FL
FL/RT
RT
RT)
This is a dual-purpose input. In the Depth Expansion Mode, this pin is
groundedtoindicatethatitisthefirstloaded(seeOperatingModes). IntheSingle
Device Mode, this pin acts as the retransmit input. The Single Device Mode is
initiated by grounding the Expansion In (
XI).
These devices can be made to retransmit data when the Retransmit
Enable control (
RT) input is pulsed LOW. A retransmit operation will set the
internal read pointer to the first location and will not affect the write pointer.
Read Enable (
R) and Write Enable (W) must be in the HIGH state during
retransmit. This feature is useful when less than 256/512/1,024/2,048/4,096/
8,192 writes are performed between resets. The retransmit feature is not
compatible with the Depth Expansion Mode and will affect the Half-Full Flag
(
HF), depending on the relative locations of the read and write pointers.
EXPANSION IN (
XI
XI)
This input is a dual-purpose pin. Expansion In (
XI) is grounded to
indicate an operation in the single device mode. Expansion In (
XI) is
connected to Expansion Out (
XO) of the previous device in the Depth
Expansion or Daisy Chain Mode.
OUTPUTS:
FULL FLAG (
FF
FF)
The Full Flag (
FF)willgoLOW,inhibitingfurtherwriteoperation,whenthe
write pointer is one location less than the read pointer, indicating that the
device is full. If the read pointer is not moved after Reset (
RS), the Full-Flag
(
FF) will go LOW after 256 writes for IDT7280, 512 writes for the IDT7281,
1,024 writes for the IDT7282, 2,048 writes for the IDT7283, 4,096 writes for
the IDT7284 and 8,192 writes for the IDT7285.
EMPTY FLAG (
EF
EF)
The Empty Flag (
EF)willgoLOW,inhibitingfurtherreadoperations,when
the read pointer is equal to the write pointer, indicating that the device is
empty.
EXPANSION OUT/HALF-FULL FLAG (
XO
XO/HF
HF
HF)
This is a dual-purpose output. In the single device mode, when Expan-
sion In (
XI) is grounded, this output acts as an indication of a half-full
memory.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (
HF)willbesetLOWandwillremainsetuntilthe
difference between the write pointer and read pointer is less than or equal
to one half of the total memory of the device. The Half-Full Flag (
HF) is then
reset by using rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (
XI) is connected to
Expansion Out (
XO) of the previous device. This output acts as a signal to
the next device in the Daisy Chain by providing a pulse to the next device
when the previous device reaches the last location of memory.
DATA OUTPUTS (Q0 – Q8)
Data outputs for 9-bit wide data. This data is in a high impedance
condition whenever Read (
R) is in a HIGH state.
相關(guān)PDF資料
PDF描述
IDT72V3640L39268BBGI 1K X 36 OTHER FIFO, 5 ns, PBGA144
IDT79R4600-133MD 64-BIT, 133 MHz, RISC PROCESSOR, PQFP208
IDT79RV4400SC-67GL447 64-BIT, 67 MHz, RISC PROCESSOR, CPGA447
IDT79RV4400SC-100GL447 64-BIT, 100 MHz, RISC PROCESSOR, CPGA447
IDT7M7004S75CH 128K X 8 EEPROM 5V MODULE, 75 ns, CPGA66
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72851L10PF 功能描述:IC FIFO SYNC 4096X18 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K(16K x 18) 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(14x14) 包裝:托盤 其它名稱:72271LA10PF
IDT72851L10PF8 功能描述:IC FIFO SYNC 4096X18 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K(16K x 18) 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(14x14) 包裝:托盤 其它名稱:72271LA10PF
IDT72851L10TF 功能描述:IC FIFO SYNC DUAL 8192X9 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K(16K x 18) 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(14x14) 包裝:托盤 其它名稱:72271LA10PF
IDT72851L10TF8 功能描述:IC FIFO SYNC DUAL 8192X9 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K(16K x 18) 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(14x14) 包裝:托盤 其它名稱:72271LA10PF
IDT72851L15PF 功能描述:IC FIFO SYNC 4096X18 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K(16K x 18) 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(14x14) 包裝:托盤 其它名稱:72271LA10PF