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參數(shù)資料
| 型號(hào)： | IDT7284L20PAI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | FIFO |
| 英文描述： | 4K X 9 BI-DIRECTIONAL FIFO, 20 ns, PDSO56 |
| 封裝： | TSSOP-56 |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大?。?/td> | 143K |
| 代理商： | IDT7284L20PAI |
1
1998
Integrated Device Technology, Inc.
DSC-3208/3
DECEMBER 1998
CMOS DUAL ASYNCHRONOUS FIFO
DUAL 256 x 9, DUAL 512 x 9,
DUAL 1,024 x 9, DUAL 2,048 x 9,
DUAL 4,096 x 9, DUAL 8,192 x 9
IDT7280
IDT7281
IDT7282
IDT7283
IDT7284
IDT7285
FEATURES:
The 7280 is equivalent to two 7200 256 x 9 FIFOs
The 7281 is equivalent to two 7201 512 x 9 FIFOs
The 7282 is equivalent to two 7202 1,024 x 9 FIFOs
The 7283 is equivalent to two 7203 2,048 x 9 FIFOs
The 7284 is equivalent to two 7204 4,096 x 9 FIFOs
The 7285 is equivalent to two 7205 8,192 x 9 FIFOs
Low power consumption
— Active: 685 mW (max.)
— Power-down: 83 mW (max.)
Ultra high speed—12 ns access time
Asynchronous and simultaneous read and write
Offers optimal combination of data capacity, small foot print
and functional flexibility
Ideal for bi-directional, width expansion, depth expansion, bus-
matching, and data sorting applications
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CMOS technology
Space-saving TSSOP
Industrial temperature range (–40oC to +85oC) is available
DESCRIPTION:
The IDT7280/7281/7282/7283/7284/7285 are dual-FIFO memories that
load and empty data on a first-in/first-out basis. These devices are functional
and compatible to two 7200/7201/7202/7203/7204/7205 FIFOs in a single
package with all associated control, data, and flag lines assigned to separate
pins. The devices use Full and Empty flags to prevent data overflow and
underflowandexpansionlogictoallowforunlimitedexpansioncapabilityinboth
word size and depth.
The reads and writes are internally sequential through the use of ring
pointers, with no address information required to load and unload data.
Data is toggled in and out of the devices through the use of the Write (
W)
and Read (
R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity
bits at the user’s option. This feature is especially useful in data commu-
nications applications where it is necessary to use a parity bit for transmis-
sion/reception error checking. It also features a Retransmit (
RT) capability
that allows for reset of the read pointer to its initial position when
RT is
pulsed LOW to allow for retransmission from the beginning of data. A Half-Full
Flag is available in the single device mode and width expansion modes.
These FIFOs are fabricated using IDT’s high-speed CMOS technology.
They are designed for those applications requiring asynchronous and
simultaneous read/writes in multiprocessing and rate buffer applications.
FUNCTIONAL BLOCK DIAGRAM
WA
WRITE
CONTROL
READ
CONTROL
RA
FLAG
LOGIC
EXPANSION
LOGIC
XIA
WRITE
POINTER
READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA
OUTPUTS
RSA
FLA/RTA
XOA/HFA
FFA
EFA
WB
WRITE
CONTROL
READ
CONTROL
RB
FLAG
LOGIC
EXPANSION
LOGIC
XIB
WRITE
POINTER
RAM
ARRAY B
256 x 9
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA
OUTPUTS
RSB
FLB/RTB
3208 drw 01
XOB/HFB
FFB
EFB
(DA0-DA8)
(DB0-DB8)
(QB0-QB8)
(QA0-QA8)
RAM
ARRAY A
256 x 9
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
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