參數(shù)資料
型號(hào)： IDT72825LB15BGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： DRAM
英文描述： CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18
中文描述： 1K X 18 BI-DIRECTIONAL FIFO, 10 ns, PBGA121
封裝： 16 X 16 MM, PLASTIC, BGA-121
文件頁(yè)數(shù)： 8/26頁(yè)
文件大小： 334K
代理商： IDT72825LB15BGI
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
8
TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE
Number of Words in FIFO
IDT72805LB
IDT72815LB
IDT72825LB
IDT72835LB
IDT72845LB
FF PAF
HF
PAE EF
0
0
0
0
0
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
H
1 to n
(1)
(n + 1) to 128
129 to (256-(m+1))
(2)
(256-m to 255
256
NOTES:
1. n = Empty offset (Default Values : IDT72805LB n=31, IDT72815LB n = 63, IDT72825LB/72835LB/72845LB n = 127)
2. m= Full offset (Default Values : IDT72805LB m=31, IDT72815LB m= 63, IDT72825LB/72835LB/72845LB m= 127)
1 to n
(1)
(n + 1) to 256
257 to (512-(m+1))
(2)
(512-m
to 511
512
1 to n
(1)
(n + 1) to 512
513 to (1,024-(m+1))
(2)
(1,024-m to 1,023
1,024
1 to n
(1)
1 to n
(1)
(n + 1) to 1,024
1,025 to (2,048-(m+1))
(2)
(2,048-m to 2,047
2,048
(n + 1) to 2,048
2,049 to (4,096-(m+1))
(2)
(4,096-m to 4,095
4,096
TABLE 2 — STATUS FLAGS FOR FWFT MODE
Number of Words in FIFO
IDT72825LB
IDT72805LB
IDT72815LB
IDT72835LB
IDT72845LB
IR
PAF HF PAE OR
0
0
0
0
0
L
L
L
L
L
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
1 to (n + 1)
(1)
(n + 2) to 129
130 to (257-(m+1))
(2)
(257-m to 256
257
NOTES:
1. n = Empty offset (Default Values : IDT72805LB n = 31, IDT72815LB n = 63, IDT72825LB/72835LB/72845LB n = 127)
2. m= Full Offset (Default Values : IDT72805LB m= 31, IDT72815LB m= 63, IDT72825LB/72835LB/72845LB m= 127)
1 to (n + 1)
(1)
(n + 2) to 257
258 to (513-(m+1))
(2)
(513-m to 512
513
1 to (n + 1)
(1)
(n + 2) to 513
514 to (1,025-(m+1))
(2)
(1,025-m to 1,024
1,025
1 to (n + 1)
(1)
(n + 2) to 1,025
1,026 to (2,049-(m+1))
(2)
(2,049-m to 2,048
2,049
1 to (n + 1)
(1)
(n + 2) to 2,049
2,050 to (4,097-(m+1))
(2)
(4,097-m to 4,096
4,097
by bringing the
LD
pin HIGH, the FIFO is returned to normal read/write
operation. When the
LD
pin and
WEN
are again set LOW, the next offset
register in sequence is written.
The contents of the offset registers can be read on the data output lines
Q
0
-Q
11
when the
LD
pin is set LOW and
REN
is set LOW. Data can then be
read on the next LOW-to-HIGH transition of RCLK. The first transition of
RCLK will present the Empty Offset value to the data output lines. The next
transition of RCLK will present the Full offset value. Offset register content
can be read out in the IDT Standard mode only. It cannot be read in the
FWFT mode.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIM-
ING SELECTION
The IDT72805LB/72815LB/72825LB/72835LB/72845LB can be config-
ured during the "Configuration at Reset" cycle described in Table 3 with
either asynchronous or synchronous timng for
PAE
and
PAF
flags.
If asynchronous
PAE
/
PAF
configuration is selected (as per Table 3), the
PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK.
PAE
is reset
to HIGH on the LOW-to-HIGH transition of WCLK. Simlarly, the
PAF
is
asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF
is reset
to HIGH on the LOW-to-HIGH transition of RCLK. For detail timng dia-
grams, see Figure 13 for asynchronous
PAE
timng and Figure 14 for
asynchronous
PAF
timng.
If synchronous
PAE
/
PAF
configuration is selected, the
PAE
is asserted
and updated on the rising edge of RCLK only and not WCLK. Simlarly,
PAF
is asserted and updated on the rising edge of WCLK only and not RCLK. For
detail timng diagrams, see Figure 22 for synchronous
PAE
timng and
Figure 23 for synchronous
PAF
timng.
REGISTER-BUFFERED FLAG OUTPUT SELECTION
The IDT72805LB/72815LB/72825LB/72835LB/72845LB can be config-
ured during the "Configuration at Reset" cycle described in Table 4 with
single, double or triple register-buffered flag output signals. The various
combinations available are described in Table 4 and Table 5. In general,
going fromsingle to double or triple buffered flag outputs removes the
possibility of metastable flag indications on boundary states (i.e, empty or
full conditions). The trade-off is the addition of clock cycle delays for the
respective flag to be asserted. Not all combinations of register-buffered flag
outputs are supported. Register-buffered outputs apply to the Empty Flag
and Full Flag only. Partial flags are not effected. Table 4 and Table 5
summarize the options available.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72825LB15PF 功能描述:IC FIFO SYNC DL 1024X18 128TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱:72271LA10PF
IDT72825LB15PF8 功能描述:IC FIFO SYNC DL 1024X18 128TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱:72271LA10PF
IDT72825LB15PFGI 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC DL 1024X18 128TQFP
IDT72825LB15PFGI8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC DL 1024X18 128TQFP
IDT72825LB15PFI 功能描述:IC FIFO SYNC DL 1024X18 128TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱:72271LA10PF
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