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參數(shù)資料
| 型號(hào)： | IDT7281L25TPI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | FIFO |
| 英文描述： | 512 X 9 OTHER FIFO, 25 ns, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大?。?/td> | 143K |
| 代理商： | IDT7281L25TPI |
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COMMERCIAL,INDUSTRIALANDMILITARY
TEMPERATURERANGES
IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
USAGE MODES:
WIDTH EXPANSION
Word width may be increased simply by connecting the corresponding
input control signals of multiple devices. Status flags (
EF, FFandHF)canbe
detected from any one device. Figure 13 demonstrates an 18-bit word width
by using two IDT7200/7201A/7202As. Any word width can be attained by
adding additional IDT7200/7201A/7202As (Figure 13).
BIDIRECTIONAL OPERATION
Applications which require data buffering between two systems (each
system capable of Read and Write operations) can be achieved by pairing
IDT7200/7201A/7202As as shown in Figure 16. Both Depth Expansion and
Width Expansion may be used in this mode.
DATA FLOW-THROUGH
Two types of flow-through modes are permitted, a read flow-through
and write flow-through mode. For the read flow-through mode (Figure 17),
the FIFO permits a reading of a single word after writing one word of data into
an empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of
W, called the first write edge, and it remains on the bus until the Rline
is raised from LOW-to-HIGH, after which the bus would go into a three-state
mode after tRHZ ns. The
EF line would have a pulse showing temporary
deassertion and then would be asserted.
In the write flow-through mode (Figure 18), the FIFO permits the writing
of a single word of data immediately after reading one word of data from a
full FIFO. The
RlinecausestheFFtobedeassertedbuttheWlinebeingLOW
causes it to be asserted again in anticipation of a new data word. On the rising
edge of
W, the new word is loaded in the FIFO. The W line must be toggled
when
FFisnotassertedtowritenewdataintheFIFOandtoincrementthewrite
pointer.
COMPOUND EXPANSION
The two expansion techniques described above can be applied together
in a straightforward manner to achieve large FIFO arrays (see Figure 15).
Figure 13. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18 FIFO Memory Used in Width Expansion Mode
Figure 12. Block Diagram of Single 256 x 9, 512 x 9, 1,024 x 9 FIFO
WRITE (
W)
DATA IN (D)
FULL FLAG (
FF)
RESET (
RS)
9
READ (
R)
9
DATA OUT (Q)
EMPTY FLAG (
EF)
RETRANSMIT (
RT)
EXPANSION IN (
XI)
(
HF)
IDT
7200/
7201A/
7202A
(HALF-FULL FLAG)
2679 drw 14
IDT
7200/
7201A/
7202A
XI
99
18
9
18
HF
9
DATA
WRITE (
W)
FULL FLAG (
FF)
RESET (
RS)
(D)
IN
READ (
R)
EMPTY FLAG (
EF)
RETRANSMIT (
RT)
DATA OUT (Q)
IDT
7200/
7201A/
7202A
2679 drw 15
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