IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
參數(shù)資料
型號(hào)： IDT723656L12PF
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 23/39頁(yè)
文件大?。?/td> 0K
描述： IC FIFO SYNC 4096X36 128QFP
標(biāo)準(zhǔn)包裝： 36
系列： 7200
功能： 同步
存儲(chǔ)容量： 147K（4K x 36）
數(shù)據(jù)速率： 83MHz
訪問(wèn)時(shí)間： 12ns
電源電壓： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤(pán)
其它名稱(chēng)： 723656L12PF
3
COMMERCIALTEMPERATURERANGE
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
Communication between each port may bypass the FIFOs via two mailbox
registers. Themailboxregisters'widthmatchestheselectedbuswidthofports
B and C. Each mailbox register has a flag (
MBF1 and MBF2) to signal when
new mail has been stored.
Two kinds of reset are available on these FIFOs: Master Reset and Partial
Reset. Master Reset initializes the read and write pointers to the first location
ofthememoryarrayandselectsserialflagprogramming,parallelflagprogram-
ming, or one of five possible default flag offset settings, 8, 16, 64, 256 or 1,024.
Each FIFO has its own, independent Master Reset pin,
MRS1 and MRS2.
Partial Reset also sets the read and write pointers to the first location of the
memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,
programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings. Each FIFO has its own, independent Partial Reset pin,
PRS1andPRS2. NotethattheRetransmitMode,RTMpinmustbeLOWatthe
point a partial reset is performed.
BothFIFO'shaveRetransmitcapability,whenaRetransmitisperformedon
a respective FIFO only the read pointer is reset to the first memory location. A
RetransmitisperformedbyusingtheRetransmitMode,RTMpininconjunction
with the Retransmit pins
RT1 or RT2, foreachrespectiveFIFO. Notethatthe
two Retransmit pins
RT1 and RT2 are muxed with the Partial Reset pins.
These devices have two modes of operation: In the IDT Standard mode, the
first word written to an empty FIFO is deposited into the memory array. A read
operation is required to access that word (along with all other words residing
in memory). In theFirstWordFallThroughmode(FWFT), the first word written
to an empty FIFO appears automatically on the outputs, no read operation
required (Nevertheless, accessing subsequent words does necessitate a
formal read request). The state of the BE/
FWFT pin during Master Reset
determines the mode in use.
EachFIFOhasacombinedEmpty/OutputReadyFlag(
EFA/ORAandEFB/
ORB) and a combined Full/Input Ready Flag (
FFA/IRA and FFC/IRC). The
EF and FF functions are selected in the IDT Standard mode. EF indicates
whether or not the FIFO memory is empty.
FF shows whether the memory is
full or not. The IR and OR functions are selected in the First Word Fall Through
mode. IR indicates whether or not the FIFO has available memory locations.
OR shows whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
Each FIFO has a programmable Almost-Empty flag (
AEA and AEB) and a
programmable Almost-Full flag (
AFAandAFC). AEAandAEB indicatewhen
aselectednumberofwordsremainintheFIFOmemory.
AFAandAFCindicate
when the FIFO contains more than a selected number of words.
FFA/IRA, FFC/IRC,AFA and AFC aretwo-stagesynchronizedtothePort
Clock that writes data into its array.
EFA/ORA,EFB/ORB, AEA,and AEBare
two-stage synchronized to the Port Clock that reads data from its array.
Programmable offsets for
AEA, AEB, AFA, AFC are loaded in parallel using
PortAorinserialviatheSDinput. Fivedefaultoffsetsettingsarealsoprovided.
The
AEA and AEB threshold can be set at 8, 16, 64, 256, and 1,024 locations
from the empty boundary and the
AFA and AFC threshold can be set at 8, 16,
64, 256 or 1,024 locations from the full boundary. All these choices are made
using the FS0, FS1 and FS2 inputs during Master Reset.
Interspersed Parity can also be selected during a Master Reset of the FIFO.
If Interspersed Parity is selected then during parallel programming of the flag
offset values, the device will ignore data line A8. If Non-Interspersed Parity is
selected then data line A8 will become a valid bit.
ALoopbackfunctionisprovidedonPortA. WhentheLoopfeatureisselected
via the
LOOPpin,thedataoutputfromFIFO2willbedirectedtothedatainput
of FIFO1. If Loop is selected and Port A is set-up for write operation via W/
RA
pin, then data output from FIFO2 will be written to FIFO1, but will not be placed
on the output Port A (A0-A35). If Port A is set-up for read operation via W/
RA
then data output from FIFO2 will be written into FIFO1 and placed onto Port A
(A0-A35). The Loop will continue to happen provided that FIFO1 is not full and
FIFO2 is not empty. If during a Loop sequence FIFO1 becomes full then any
data that continues to be read out from FIFO2 will only be placed on the Port
A (A0-A35) lines, provided that Port A is set-up for read operation. If during
a Loop sequence the FIFO2 becomes empty, then the last word from FIFO2
willcontinuetobeclockedintoFIFO1untilFIFO1becomesfulloruntiltheLoop
function is stopped. The Loop feature can be useful when performing system
debugging and remote loopbacks.
TwoormoreFIFOsmaybeusedinparalleltocreatewiderdatapaths. Such
a width expansion requires no additional, external components. Furthermore,
two IDT723656/723666/723676 FIFOs can be combined with unidirectional
FIFOs capable of First Word Fall Through timing (i.e. the SuperSync FIFO
family) to form a depth expansion.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption(ICC)isataminimum. Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
The IDT723656/723666/723676 are characterized for operation from 0
°C
to 70
°C. Industrialtemperaturerange(-40°Cto+85°C)isavailablebyspecial
order. They are fabricated using IDT’s high speed, submicron CMOS
technology.
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IDT723656L12PF8 功能描述:IC FIFO SYNC 4096X36 128QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
IDT723656L15PF 功能描述:IC FIFO SYNC 4096X36 128QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
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IDT723662L12PF 功能描述:IC FIFO BI SYNC 8192X36 120QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
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