19
COMMERCIALTEMPERATURERANGE
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
NOTES:
1.
PRS2 and MBC must be HIGH during Master Reset until the rising edge of FFC/IRC goes HIGH.
2. If BE/
FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than in this case where BE/FWFT is LOW.
3.
MRS2 must toggle simultaneously with MRS1.
Figure 5. FIFO2 Master Reset and Loading X2 and Y2 with a Preset Value of Eight (IDT Standard and FWFT Modes)
Figure 4. FIFO1 Master Reset and Loading X1 and Y1 with a Preset Value of Eight (IDT Standard and FWFT Modes)
NOTES:
1.
PRS1 and MBC must be HIGH during Master Reset until the rising edge of FFA/IRA goes HIGH.
2. If BE/
FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
CLKA
MRS1
FFA/IRA
AEB
AFA
MBF1
CLKB
EFB/ORB
FS2,FS1
,FS0
5611 drw 05
tRSTS
tRSTH
tFSH
tFSS
tWFF
tREF
tRSF
0,1
tRSF
BE
BE/FWFT
FWFT
tBES
tBEH
12
tFWS
(2)
LOOP
RTM
LOW
HIGH
CLKC
MRS2(3)
FFC/IRC
AEA
AFC
MBF2
CLKA
EFA/ORA
FS2,FS1
,FS0
5611 drw 06
tRSTS
tRSTH
tFSH
tFSS
tWFF
tREF
tRSF
0,1
tRSF
BE
BE/FWFT
FWFT
tBES
tBEH
1
2
tFWS
(2)
LOOP
RTM
LOW
HIGH