參數(shù)資料
型號(hào)： IDT723646L15PF
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 5/35頁(yè)
文件大小： 0K
描述： IC FIFO SYNC 2048X36 128QFP
標(biāo)準(zhǔn)包裝： 72
系列： 7200
功能： 同步
存儲(chǔ)容量： 72K（2K x 36）
數(shù)據(jù)速率： 67MHz
訪問(wèn)時(shí)間： 15ns
電源電壓： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤(pán)
其它名稱： 723646L15PF
13
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TABLE 5 — FIFO1 FLAG OPERATION (IDT Standard and FWFT modes)
TABLE 6 — FIFO2 FLAG OPERATION (IDT Standard and FWFT modes)
Synchronized
Number of Words in FIFO Memory(1,2)
to CLKB
to CLKA
IDT723626(3)
IDT723636(3)
IDT723646(3)
EFB/ORB
AEB
AFA
FFA/IRA
00
0
L
H
1 to X1
H
L
H
(X1+1) to [256-(Y1+1)]
(X1+1) to [512-(Y1+1)]
(X1+1) to [1,024-(Y1+1)]
H
(256-Y1) to 255
(512-Y1) to 511
(1,024-Y1) to 1,023
H
L
H
256
512
1,024
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register
(no read operation necessary), it is not included in the FIFO memory count.
3. X1 is the almost-empty offset for FIFO1 used by
AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.
4. The ORB and IRA functions are active during FWFT mode; the
EFB and FFA functions are active in IDT Standard mode.
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation
necessary), it is not included in the FIFO memory count.
3. X2 is the almost-empty offset for FIFO2 used by
AEA. Y2 is the almost-full offset for FIFO2 used by AFC. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.
4. The ORA and IRC functions are active during FWFT mode; the
EFA and FFC functions are active in IDT Standard mode.
Synchronized
Number of Words in FIFO Memory(1,2)
to CLKA
to CLKC
IDT723626(3)
IDT723636(3)
IDT723646(3)
EFA/ORA
AEA
AFC
FFC/IRC
00
0
L
H
1 to X2
H
L
H
(X2+1) to [256-(Y2+1)]
(X2+1) to [512-(Y2+1)]
(X2+1) to [1,024-(Y2+1)]
H
(256-Y2) to 255
(512-Y2) to 511
(1,024-Y2) to 1,023
H
L
H
256
512
1,024
H
L
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through at least two flip-flop
stages. This is done to improve flag signal reliability by reducing the probability
of metastable events when CLKA operates asynchronously with respect to
either CLKB or CLKC.
EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to
CLKA.
EFB/ORB and AEB are synchronized to CLKB. FFC/IRC and AFC are
synchronized to CLKC. Tables 5 and 6 show the relationship of each port flag
to FIFO1 and FIFO2.
EMPTY/OUTPUT READY FLAGS (
EFA/ORA,EFB/ORB)
Thesearedualpurposeflags.IntheFWFTmode,theOutputReady(ORA,
ORB) function is selected. When the Output Ready flag is HIGH, new data is
present in the FIFO output register. When the Output Ready flag is LOW, the
previous data word is present in the FIFO output register and attempted FIFO
reads are ignored.
IntheIDTStandardmode,theEmptyFlag(
EFA,EFB)functionisselected.
When the Empty Flag is HIGH, data is available in the FIFO’s RAM memory
for reading to the output register. When the Empty Flag is LOW, the previous
data word is present in the FIFO output register and attempted FIFO reads are
ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the port clock
that reads data from its array. For both the FWFT and IDT Standard modes, the
FIFO read pointer is incremented each time a new word is clocked to its output
register. The state machine that controls an Output Ready flag monitors a write
pointer and read pointer comparator that indicates when the FIFO memory
status is empty, empty+1, or empty+2.
In FWFT mode, from the time a word is written to a FIFO, it can be shifted
totheFIFOoutputregisterinaminimumofthreecyclesoftheOutputReadyflag
synchronizing clock. Therefore, an Output Ready flag is LOW if a word in
memory is the next data to be sent to the FlFO output register and three cycles
of the port clock that reads data from the FIFO have not elapsed since the time
thewordwaswritten.TheOutputReadyflagoftheFIFOremainsLOWuntilthe
thirdLOW-to-HIGHtransitionofthesynchronizingclockoccurs,simultaneously
forcing the Output Ready flag HIGH and shifting the word to the FIFO output
register.
In IDT Standard mode, from the time a word is written to a FIFO, the
Empty Flag will indicate the presence of data available for reading in a
minimum of two cycles of the Empty Flag synchronizing clock. Therefore,
anEmptyFlagisLOWifawordinmemoryisthenextdatatobesenttotheFlFO
output register and two cycles of the port Clock that reads data from the FIFO
have not elapsed since the time the word was written. The Empty Flag of the
FIFO remains LOW until the second LOW-to-HIGH transition of the synchro-
nizing clock occurs, forcing the Empty Flag HIGH; only then can data be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle
can be the first synchronization cycle (see Figures 16, 17, 18 and 19).
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