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參數(shù)資料
| 型號： | IDT723642L30PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC 0 to 70 |
| 中文描述： | 1K X 36 BI-DIRECTIONAL FIFO, 15 ns, PQFP120 |
| 封裝： | TQFP-120 |
| 文件頁數(shù)： | 21/26頁 |
| 文件大?。?/td> | 294K |
| 代理商： | IDT723642L30PF |
5.22
21
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
AEA
CLKB
ENA
3022 drw 15
ENB
CLKA
2
1
t
ENS
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENS
t
ENH
(X2+1) Words in FIFO2
X2 Words in FIFO2
(1)
Figure 13. Timing for
AFA
when FIFO1 is Almost Full.
NOTES:
1. t
SKEW2
is the minimum time between a rising CLKA edge and a rising CLKB edge for
AFA
to transition HIGH in the next CLKA cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than t
SKEW2
, then
AFA
may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (
CSA
= LOW, W/
R
A = HIGH, MBA = LOW), FIFO1 read (
CSB
= LOW,
W
/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has
been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the 723622, 512 for the 723632, 1024 for the 723642.
AFA
CLKA
ENB
3022 drw 16
ENA
CLKB
1
2
t
SKEW2
t
ENS
t
ENH
t
PAF
t
ENS
t
ENH
t
PAF
[D-(Y1+1)] Words in FIFO1
(D-Y1) Words in FIFO1
(1)
Figure 12. Timing for
AEA
when FIFO2 is Almost Empty.
NOTES:
1. t
SKEW2
is the minimum time between a rising CLKB edge and a rising CLKA edge for
AEA
to transition HIGH in the next CLKA cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than t
SKEW2
, then
AEA
may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (
CSB
= LOW,
W
/RB = LOW, MBB = LOW), FIFO2 read (
CSA
= LOW, W/
R
A = LOW, MBA = LOW). Data in the FIFO2 output register has
been read from the FIFO.
相關PDF資料 |
PDF描述 |
|---|---|
| IDT723642L30PQF | HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC 0 to 70 |
| IDT723641 | Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC -40 to 105 |
| IDT723631L15PF | CMOS SyncFIFOO 512 x 36, 1024 x 36, 2048 x 36 |
| IDT723631L15PQF | CMOS SyncFIFOO 512 x 36, 1024 x 36, 2048 x 36 |
| IDT723631 | Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT723643L12PF | 功能描述:IC FIFO SYNC 1024X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723643L12PF8 | 功能描述:IC FIFO SYNC 1024X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723643L12PFG | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 128-Pin TQFP |
| IDT723643L15PF | 功能描述:IC FIFO SYNC 1024X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723643L15PF8 | 功能描述:IC FIFO SYNC 1024X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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