- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9922 > IDT723642L15PQF (IDT, Integrated Device Technology Inc)IC FIFO SYNC 2048X36 132QFP PDF資料下載
參數(shù)資料
| 型號： | IDT723642L15PQF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 2/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 2048X36 132QFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 72K（2K x 36） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問時間： | 15ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 供應(yīng)商設(shè)備封裝： | 132-PQFP（24.13x24.13） |
| 包裝： | 托盤 |
| 其它名稱： | 723642L15PQF |
10
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
— PARALLEL LOAD FROM PORT A
ToprogramtheX1,X2,Y1,andY2registersfromportA,bothFlFOsshould
be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH
transition of the Reset inputs. After this reset is complete, the first four writes to
FIFO1 do not store data in the FIFO memory but load the offset registers in the
order Y1, X1, Y2, X2. The port A data inputs used by the offset registers are
(A7-A0), (A8-A0), or (A9-A0) for the IDT723622, IDT723632, or IDT723642,
respectively. The highest numbered input is used as the most significant bit of
the binary number in each case. Valid programming values for the registers
ranges from 1 to 252 for the IDT723622; 1 to 508 for the IDT723632; and 1 to
1,020fortheIDT723642. Afteralltheoffsetregistersareprogrammedfromport
A, the port B Input Ready flag (IRB) is set HIGH, and both FIFOs begin normal
operation.SeeFigure3forrelevantoffsetregisterparallelprogrammingtiming
diagram.
FIFO WRITE/READ OPERATION
The state of the port A data (A0-A35) outputs is controlled by port A Chip
Select (
CSA) and port A Write/Read select (W/RA). The A0-A35 outputs are
in the high-impedance state when either
CSA or W/RA is HIGH. The A0-A35
outputs are active when both
CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when
CSA is LOW, W/RA is HIGH, ENA is HIGH , MBA is
LOW, and IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a
LOW-to-HIGH transition of CLKA when
CSA is LOW, W/RA is LOW, ENA is
HIGH, MBA is LOW, and ORA is HIGH (see Table 2). FIFO reads and writes
on port A are independent of any concurrent port B operation. Write and Read
cycle timing diagrams for port A can be found in Figure 4 and 7.
TheportBcontrolsignalsareidenticaltothoseofportAwiththeexception
thattheportBWrite/Readselect(
W/RB)istheinverseoftheportAWrite/Read
select(W/
RA).ThestateoftheportBdata(B0-B35)outputsiscontrolledbythe
port B Chip Select (
CSB) and port B Write/Read select (W/RB). The B0-B35
outputs are in the high-impedance state when either
CSB is HIGH orW/RBis
LOW. The B0-B35 outputs are active when
CSB is LOW and W/RB is HIGH.
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
transitionofCLKBwhen
CSBisLOW,W/RBisLOW,ENBisHIGH,MBBisLOW,
and IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a LOW-
to-HIGH transition of CLKB when
CSB is LOW,W/RBisHIGH,ENBisHIGH,
MBB is LOW, and ORB is HIGH (see Table 3) . FIFO reads and writes on port
B are independent of any concurrent port A operation. Write and Read cycle
timing diagrams for port B can be found in Figure 5 and 6.
SIGNAL DESCRIPTION
RESET
After power up, a Master Reset operation must be performed by
providingaLOWpulseto
RSTIandRST2simultaneously. Afterwards,theFIFO
memories of the IDT723622/723632/723642 are reset separately by taking
their Reset (
RST1,RST2)inputsLOWforatleastfourportAClock(CLKA)and
fourportBClock(CLKB)LOW-to-HIGHtransitions.TheResetinputscanswitch
asynchronouslytotheclocks.AFIFOresetinitializestheinternalreadandwrite
pointers and forces the Input Ready flag (IRA, IRB) LOW, the Output Ready
flag(ORA,ORB)LOW,theAlmost-Emptyflag(
AEA,AEB)LOW,andtheAlmost-
Full flag (
AFA, AFB) HIGH. Resetting a FIFO also forces the Mailbox Flag
(
MBF1, MBF2) of the parallel mailbox register HIGH. After a FlFO is reset, its
Input Ready flag is set HIGH after two clock cycles to begin normal operation.
A LOW-to-HIGH transition on a FlFO Reset (
RST1, RST2)inputlatches
the value of the Flag Select (FS0, FS1) inputs for choosing the Almost-Full and
Almost-Empty offset programming method (for details see Table 1, Flag
Programming and the Almost-Empty Flag and Almost-Full Flag Offset
Programmingsectionthatfollows).TherelevantFIFOResettimingdiagramcan
be found in Figure 2.
ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET PRO-
GRAMMING
Four registers in these devices are used to hold the offset values for
the Almost-Empty and Almost-Full flags. The port B Almost-Empty flag (
AEB)
OffsetregisterislabeledX1andtheportAAlmost-Emptyflag(
AEA)Offsetregister
islabeledX2.TheportAAlmost-Fullflag(
AFA)OffsetregisterislabeledY1and
theportBAlmost-Fullflag(
AFB)OffsetregisterislabeledY2.Theindexofeach
register name corresponds to its FIFO number. The offset registers can be
loadedwithpresetvaluesduringtheresetofaFIFOortheycanbeprogrammed
from port A (see Table 1).
— PRESET VALUES
ToloadtheFIFO'sAlmost-EmptyflagandAlmost-FullflagOffsetregisters
withoneofthethreepresetvalueslistedinTable1,atleastoneoftheflagselect
inputs must be HIGH during the LOW-to-HIGH transition of its Reset input. For
example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be
HIGHwhenFlFO1Reset(
RST1)returnsHIGH.Flagoffsetregistersassociated
withFIFO2areloadedwithoneofthepresetvaluesinthesamewaywithFIFO2
Reset (
RST2) toggled simultaneously with FIFO1 Reset (RST1). For preset
value loading timing diagram, see Figure 2.
FS1
FS0
RST1
RST2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
HH
↑
X64
X
HH
X
↑
X64
HL
↑
X16
X
HL
X
↑
X16
LH
↑
X8
X
LH
X
↑
X8
LL
↑↑
Programmed from port A
NOTES:
1. X1 register holds the offset for
AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for
AEA; Y2 register holds the offset for AFB.
TABLE 1 — FLAG PROGRAMMING
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V24B24M250B2 | CONVERTER MOD DC/DC 24V 250W |
| ISL32172EFBZ-T | IC XMITTER ESD RS422 LP 16-SOIC |
| VE-BWP-MW-F3 | CONVERTER MOD DC/DC 13.8V 100W |
| ISL3232EIRZ-T | IC XMITTER/RCVR ESD RS232 16-QFN |
| VE-BWP-MW-F2 | CONVERTER MOD DC/DC 13.8V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT723642L15PQFGI | 功能描述:IC FIFO SYNC 2048X36 132QFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723643L12PF | 功能描述:IC FIFO SYNC 1024X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723643L12PF8 | 功能描述:IC FIFO SYNC 1024X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723643L12PFG | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 128-Pin TQFP |
| IDT723643L15PF | 功能描述:IC FIFO SYNC 1024X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。