參數(shù)資料
型號: IDT723642L15PQF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/25頁
文件大?。?/td> 0K
描述: IC FIFO SYNC 2048X36 132QFP
標準包裝: 36
系列: 7200
功能: 同步
存儲容量: 72K(2K x 36)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 132-BQFP 緩沖式
供應(yīng)商設(shè)備封裝: 132-PQFP(24.13x24.13)
包裝: 托盤
其它名稱: 723642L15PQF
1
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3022/5
FEBRUARY 2009
CMOS SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2,
1,024 x 36 x 2
IDT723622
IDT723632
IDT723642
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FEATURES:
Memory storage capacity:
IDT723622
256 x 36 x 2
IDT723632
512 x 36 x 2
IDT723642
1,024 x 36 x 2
Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Two independent clocked FIFOs buffering data in opposite
directions
Mailbox bypass register for each FIFO
Programmable Almost-Full and Almost-Empty flags
Microprocessor Interface Control Logic
IRA, ORA, AEA, and AFA flags synchronized by CLKA
IRB, ORB, AEB, and AFB flags synchronized by CLKB
Supports clock frequencies up to 83MHz
Fast access times of 8ns
Available in 132-pin Plastic Quad Flatpack (PQFP) or space-
saving 120-pin Thin Quad Flatpack (TQFP)
Low-power 0.8-Micron Advanced CMOS technology
Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
Greenpartsavailable,seeorderinginformation
DESCRIPTION:
The IDT723622/723632/723642 are a monolithic, high-speed, low-power,
CMOS Bidirectional SyncFIFO (clocked) memory which supports clock fre-
quencies up to 83MHz and have read access times as fast as 8ns. Two
independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board each chip
buffer data in opposite directions. Communication between each port may
bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has
a flag to signal when new mail has been stored.
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
Mail 1
Register
Programmable Flag
Offset Registers
Input
Register
Output
Register
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
Input
Register
Output
Register
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
RST1
Mail 2
Register
MBF2
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
FIFO2,
Mail2
Reset
Logic
RST2
MBF1
FIFO 1
FIFO 2
10
ORB
AEB
36
IRB
AFB
B0 - B35
IRA
AFA
FS0
FS1
A0 - A35
ORA
AEA
3022 drw 01
36
FUNCTIONAL BLOCK DIAGRAM
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IDT723643L12PF8 功能描述:IC FIFO SYNC 1024X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K(16K x 18) 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(14x14) 包裝:托盤 其它名稱:72271LA10PF
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