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參數(shù)資料
| 型號： | IDT723642L15PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 2048X36 120QFP |
| 標準包裝： | 45 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 72K（2K x 36） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問時間： | 15ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應商設備封裝： | 120-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 723642L15PF |
13
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
in memory to [256/512/1,024-(Y+1)]. Otherwise, the subsequent synchroniz-
ing clock cycle may be the first synchronization cycle (see Figures 14 and 15).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
information between port A and port B without putting it in queue. The
Mailbox select (MBA, MBB) inputs choose between a mail register and a
FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA
writesA0-A35datatothemail1registerwhenaportAWriteisselectedby
CSA,
W/
RA,andENAandwithMBAHIGH.ALOW-to-HIGHtransitiononCLKBwrites
B0-B35 data to the mail2 register when a port B Write is selected by
CSB, W/
RB, and ENB and with MBB HIGH. Writing data to a mail register sets its
corresponding flag (
MBF1orMBF2)LOW.Attemptedwritestoamailregister
are ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus comes from
the FIFO output register when the port Mailbox select input is LOW and from
the mail register when the port-mailbox select input is HIGH. The Mail1
RegisterFlag(
MBF1)issetHIGHbyaLOW-to-HIGHtransitiononCLKBwhen
a port B Read is selected by
CSB, W/RB, and ENB and with MBB HIGH. The
Mail2RegisterFlag(
MBF2)issetHIGHbyaLOW-to-HIGHtransitiononCLKA
when a port A read is selected by
CSA, W/RA, and ENA and with MBA HIGH.
The data in a mail register remains intact after it is read and changes only when
newdataiswrittentotheregister.FormailregisterandMailRegisterflagtiming
diagrams, see Figure 16 and 17.
ALMOST-FULL FLAGS (
AFA, AFB)
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
data to its array. The state machine that controls an Almost-Full flag monitors a
writepointerandreadpointercomparatorthatindicateswhentheFIFOmemory
statusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstateisdefined
by the contents of register Y1 for
AFAandregisterY2forAFB.Theseregisters
are loaded with preset values during a FlFO reset or programmed from port
A (see Almost-Empty flag and Almost-Full flag offset programming section).
AnAlmost-FullflagisLOWwhenthenumberofwordsinitsFIFOisgreaterthan
or equal to (256-Y), (512-Y), or (1,024-Y) for the IDT723622, IDT723632, or
IDT723642respectively. AnAlmost-FullflagisHIGHwhenthenumberofwords
in its FIFO is less than or equal to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)]
for the IDT723622, IDT723632, or IDT723642 respectively. Note that a data
word present in the FIFO output register has been read from memory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock
are required after a FIFO read for its Almost-Full flag to reflect the new level of
fill. Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-(Y+1)]
or less words remains LOW if two cycles of its synchronizing clock have not
elapsed since the read that reduced the number of words in memory to [256/
512/1,024-(Y+1)]. AnAlmost-FullflagissetHIGHbythesecondLOW-to-HIGH
transitionofitssynchronizingclockaftertheFIFOreadthatreducesthenumber
ofwordsinmemoryto[256/512/1,024-(Y+1)]. ALOW-to-HIGHtransitionofan
Almost-Full flag synchronizing clock begins the first synchronization cycle if it
occursattimetSKEW2orgreaterafterthereadthatreducesthenumberofwords
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT723642L15PF8 | 功能描述:IC FIFO SYNC 2048X36 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723642L15PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 256X36X2 120TQFP |
| IDT723642L15PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 256X36X2 120TQFP |
| IDT723642L15PQF | 功能描述:IC FIFO SYNC 2048X36 132QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723642L15PQFGI | 功能描述:IC FIFO SYNC 2048X36 132QFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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