參數(shù)資料
型號: IDT723642L15PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: Quad, High Slew Rate, Single-Supply, Op Amp 14-TSSOP -40 to 105
中文描述: 1K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP120
封裝: TQFP-120
文件頁數(shù): 5/26頁
文件大小: 294K
代理商: IDT723642L15PF
5.22
5
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
Symbol
Name
I/O
Description
MBB
Port-B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a port-B read or
write operation. When the B0-B35 outputs are active, a HIGH level on
MBB selects data from the mail1 register or output and a LOW level selects
FIFO1 output-register data for output.
MBF1
is set LOW by a LOW-to-HIGH transition of CLKA that writes data
to the mail1 register. Writes to the mail1 register are inhibited while
MBF1
is
LOW.
MBF1
is set HIGH by a LOW-to-HIGH transition of CLKB when a port-B
read is selected and MBB is HIGH.
MBF1
is set HIGH when FIFO1 is reset.
MBF2
is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the
mail2 register. Writes to the mail2 register are inhibited while
MBF2
is LOW.
MBF2
is set HIGH by a LOW-to-HIGH transition of CLKA when a port-A read is
selected and MBA is HIGH.
MBF2
is also set HIGH when FIFO2 is reset.
ORA is synchronized to the LOW-to-HIGH transition of CLKA. When ORA is
LOW, FIFO2 is empty and reads from its memory are disabled. Ready data
is present on the output register of FIFO2 when ORA is HIGH. ORA is
forced LOW when FlFO2 is reset and goes HIGH on the third LOW-to-HIGH
transition of CLKA after a word is loaded to empty memory.
ORB is synchronized to the LOW-to-HIGH transition of CLKB. When ORB
is LOW, FlFO1 is empty and reads from its memory are disabled. Ready data
is present on the output register of FIFO1 when ORB is HIGH. ORB is forced LOW
when FIFO1 is reset and goes HIGH on the third LOW-to-HIGH transition of CLKB
after a word is loaded to empty memory.
To reset FIFO1, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH
transitions of CLKB must occur while
RST1
is LOW. The LOW-to-HIGH transition
of
RST1
latches the status of FSO and FS1 for
AFA
and
AEB
offset selection.
FIFO1 must be reset upon power up before data is written to its RAM.
To reset FIFO2, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH
transitions of CLKB must occur while
RST2
is LOW. The LOW-to-HIGH transition
of
RST2
latches the status of FSO and FS1 for
AFB
and
AEA
offset selection.
FIFO2 must be reset upon power up before data is written to its RAM.
A HIGH selects a write operation and a LOW selects a read operation on port A
for a LOW-to-HIGH transition of CLKA. The AO-A35 outputs are in
the HIGH impedance state when W/
R
A is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on port B
for a LOW-to-HIGH transition of CLKB. The BO-B35 outputs are in the HIGH
impedance state when
W
/RB is LOW.
MBF1
Mail1 Register
Flag
O
MBF2
Mail2 Register
Flag
O
ORA
Output-Ready
Flag
O
(Port A)
ORB
Output-Ready
Flag
O
(Port B)
RST1
FIFO1 Reset
I
RST2
FIFO2 Reset
I
W/
R
A
Port-A Write/
Read Select
I
W
/RB
Port-B Write/
Read Select
I
PIN DESCRIPTIONS (CONT.)
相關(guān)PDF資料
PDF描述
IDT723642L15PQF HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC 0 to 70
IDT723642L20PF HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC 0 to 70
IDT723642L20PQF HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC 0 to 70
IDT723642L30PF HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC 0 to 70
IDT723642L30PQF HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC 0 to 70
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