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參數資料
| 型號： | IDT723642L15PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Quad, High Slew Rate, Single-Supply, Op Amp 14-TSSOP -40 to 105 |
| 中文描述： | 1K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP120 |
| 封裝： | TQFP-120 |
| 文件頁數： | 12/26頁 |
| 文件大?。?/td> | 294K |
| 代理商： | IDT723642L15PF |
5.22
12
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
occurs, simultaneously forcing the output-ready flag HIGH
and shifting the word to the FIFO output register.
A LOW-to-HIGH transition on an output-ready flag syn-
chronizing clock begins the first synchronization cycle of a
write if the clock transition occurs at time t
SKEW1
or greater
after the write. Otherwise, the subsequent clock cycle can be
the first synchronization cycle (see Figures 7 and 8).
INPUT-READY FLAGS (IRA, IRB)
The input-ready flag of a FlFO is synchronized to the port
clock that writes data to its array. When the input-ready flag
is HIGH, a memory location is free in the SRAM to receive new
data. No memory locations are free when the input-ready flag
is LOW and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pointer is
incremented. The state machine that controls an input-ready
flag monitors a write pointer and read pointer comparator that
indicates when the FlFO SRAM status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory
location is ready to be written in a minimum of two cycles of the
S
ynchronized
to CLKB
ORB
L
H
H
H
Synchronized
to CLKA
AFA
H
H
H
L
Number of Words in FIFO
IDT723632
(1,2)
0
1 to X1
(X1+1) to [512-(Y1+1)]
(512-Y1) to 511
IDT723622
(1,2)
0
1 to X1
(X1+1) to [256-(Y1+1)]
(256-Y1) to 255
IDT723642
(1,2)
0
1 to X1
(X1+1) to [1024-(Y1+1)]
(1024-Y1) to 1023
AEB
L
L
H
H
IRA
H
H
H
H
256
512
1024
H
H
L
L
Table 4. FIF01 Flag Operatlon
Notes:
1.
X1 is the almost-empty offset for FIFO1 used by
AEB
. Y1 is the almost-full offset for FIFO1 used by
AFA
. Both X1
and Y1 are selected during a reset of FIFO1 or programmed from port A.
When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2.
S
ynchronized
to CLKA
ORA
L
H
H
H
Synchronized
to CLKB
AFB
H
H
H
L
Number of Words in FIFO
IDT723632
(1,2)
0
1 to X2
(X2+1) to [512-(Y2+1)]
(512-Y2) to 511
IDT723622
(1,2)
0
1 to X2
(X2+1) to [256-(Y2+1)]
(256-Y2) to 255
IDT723642
(1,2)
0
1 to X2
(X2+1) to [1024-(Y2+1)]
(1024-Y2) to 1023
AEA
L
L
H
H
IRB
H
H
H
H
256
512
1024
H
H
L
L
Table 5. FIF02 Flag Operatlon
Notes:
1. X2 is the almost-empty offset for FIFO2 used by
AEA
. Y2 is the almost-full offset for FIFO2 used by
AFB
. Both X2 and
Y2 are selected
during a reset of FIFO2 or programmed from port A.
2. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
OUTPUT-READY FLAGS (ORA, ORB)
The output-ready flag of a FIFO is synchronized to the port
clock that reads data from its array. When the output-ready
flag is HIGH, new data is present in the FIFO output register.
When the output-ready flag is LOW, the previous data word is
present in the FIFO output register and attempted FIFO reads
are ignored.
A FIFO read pointer is incremented each time a new word
is clocked to its output register. The state machine that
controls an output-ready flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM
status is empty, empty+1, or empty+2. From the time a word
is written to a FIFO, it can be shifted to the FIFO output register
in a minimum of three cycles of the output-ready flag synchro-
nizing clock. Therefore, an output-ready flag is LOW if a word
in memory is the next data to be sent to the FlFO output
register and three cycles of the port Clock that reads data from
the FIFO have not elapsed since the time the word was
written. The output-ready flag of the FIFO remains LOW until
the third LOW-to-HIGH transition of the synchronizing clock
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相關代理商/技術參數 |
參數描述 |
|---|---|
| IDT723642L15PF8 | 功能描述:IC FIFO SYNC 2048X36 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數據速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723642L15PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 256X36X2 120TQFP |
| IDT723642L15PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 256X36X2 120TQFP |
| IDT723642L15PQF | 功能描述:IC FIFO SYNC 2048X36 132QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數據速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723642L15PQFGI | 功能描述:IC FIFO SYNC 2048X36 132QFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數據速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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