參數(shù)資料
型號(hào): IDT723631L30PQF
廠(chǎng)商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: Quad, High Slew Rate, Single-Supply, Op Amp 14-TSSOP 0 to 70
中文描述: 512 X 36 OTHER FIFO, 15 ns, PQFP132
封裝: PLASTIC, QFP-132
文件頁(yè)數(shù): 16/23頁(yè)
文件大?。?/td> 269K
代理商: IDT723631L30PQF
16
IDT723631/723641/723651 CMOS SyncFIFO
512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
Figure 7. IR Flag Timing and First Available Write when the FIFO is Full
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for
AE
to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW2, then
AE
may transition HIGH one CLKB cycle later than shown.
2. FIFO write (
CSA
= LOW, W/
R
A = HIGH, MBA = LOW), FIFO read (
CSB
= LOW,
W
/RB = HIGH, MBB = LOW).
Figure 8. Timing for
AE
when FIFO is Almost Empty
CSB
OR
W
/RB
MBB
ENB
B0 -B35
CLKB
IR
CLKA
CSA
W
R
A
A0 - A35
MBA
ENA
3023 drw 10
1
2
t
CLK
t
CLKH
t
CLKL
t
ENS1
t
ENH1
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
PIR
t
PIR
t
ENS2
t
ENS1
t
DS
t
ENH2
t
ENH1
t
DH
Previous Word in FIFO Output Register
Next Word From FIFO
LOW
HIGH
LOW
HIGH
LOW
HIGH
(1)
FIFO Full
Write
AE
CLKA
ENB
ENA
CLKB
3023 drw 11
2
1
t
ENS1
t
ENH1
t
SKEW2
t
PAE
t
PAE
t
ENS1
t
ENH1
X Word in FIFO
(X+1) Words in FIFO
(1)
相關(guān)PDF資料
PDF描述
IDT723641L15PF Quad, High Slew Rate, Single-Supply, Op Amp 14-PDIP -40 to 105
IDT723651L30PQF HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC -40 to 105
IDT723641L15PQF Quad, High Slew Rate, Single-Supply, Op Amp 14-PDIP -40 to 105
IDT723641L20PF Quad, High Slew Rate, Single-Supply, Op Amp 14-TSSOP -40 to 105
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