參數(shù)資料
型號(hào)： IDT723613L30PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： DRAM
英文描述： CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36
中文描述： 64 X 36 OTHER FIFO, 15 ns, PQFP120
封裝： TQFP-120
文件頁(yè)數(shù)： 5/26頁(yè)
文件大?。?/td> 193K
代理商： IDT723613L30PF
5
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
Symbol
PGA
Name
I/O
I
Description
Port A Parity Generation
Parity is generated for data reads fromthe mail2 register when PGA is HIGH. The type of parity
generated is selected by the state of the ODD/
EVEN
input. Bytes are organized at A
0
-A
8
, A
9
-A
17
,
A
18
-A
26
, and A
27
-A
35
. The generated parity bits are output in the most significant bit of each byte.
Parity is generated for data reads fromport B when PGB is HIGH. The type of parity generated is
selected by the state of the ODD/
EVEN
input. Bytes are organized as B
0
-B
8
, B
9
-B
17
, B
18
-B
26
, and
B
27
-B
35
. The generated parity bits are output in the most significant bit of each byte.
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while
RST
is LOW. This sets the
AF
,
MBF1
, and
MBF2
flags HIGH and the
EF
,
AE
, and
FF
flags LOW. The LOW-to-HIGH transition of
RST
latches the status of the FS
1
and FS
0
inputs to select
Almost-Full flag and Almost-Empty flag offset.
A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and
BE
, and the following LOW-to
HIGH transition of CLKB implements the latched states as a port B bus size. Port B bus sizes can be
long word, word, or byte. A HIGH on both SIZ0 and SIZ1 accesses the mailbox registers for a port B 36-bit
write or read.
At the beginning of each long word FIFO read, one of four modes of byte-order swapping is selected by
SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte order
swapping is possible with any bus-size selection.
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
transition of CLKA. The A
0
-A
35
outputs are in the high-impedance state when W/
R
A is HIGH.
A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH
transition of CLKB. The B
0
-B
35
outputs are in the high-impedance state when W/
R
B is HIGH.
PGB
Port B Parity
I
RST
Reset
I
SIZ0,
SIZ1
Port B Bus Size Selects
I
(Port B)
SW0,
SW1
Port B Byte Swap Selects
I
(Port B)
W/
R
A
Port A Write/Read Select
Select
Port B Write/Read Select
I
W/
R
B
I
PIN DESCRIPTION (CONTINUED)
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