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參數(shù)資料
| 型號(hào)： | IDT72141 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
| 中文描述： | CMOS并行到串行FIFO的2048 × 9 4096 × 9 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 126K |
| 代理商： | IDT72141 |
5.34
5
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure A
2751 tbl 08
or equivalent circuit
Figure 1. Reset
Serial Data Output
The serial data is output on the SO pin. The data is clocked
out on the rising edge of SOCP providing the Empty Flag (
EF
)
is not asserted. If the Empty Flag is asserted then the next data
word is inhibited from moving to the output register and being
clocked out by SOCP. NOTE: SOCP should not be clocked
once the last bit of the last word has been clocked out. If it is,
then two things will occur. One, the SO pin will go High-Z and
two, SOCP will be out of sync with Next Read (
NR
).
The serial word is shifted out Least Significant Bit first, that
is the first bit will be D0, then D1 and so on up to the serial word
width. The serial word width must be programmed by connect-
ing the appropriate Data Set line (Q4, Q6, Q7 or Q8) to the
NR
input. The Data Set lines are taps off a digital delay line.
Selecting one of these taps, programs the width of the serial
word to be read and shifted out.
FUNCTIONAL DESCRIPTION
Parallel Data Input
The data is written into the FIFO in parallel through the
D
0-8
input data lines. A write cycle is initiated on the falling
edge of the Write (
W
) signal provided the Full Flag (
FF
) is not
asserted. If the
W
signal changes from HIGH-to-LOW and the
Full-Flag (
FF
) is already set, the write line is inhibited internally
from incrementing the write pointer and no write operation
occurs.
Data set-up and hold times must be met with respect to the
rising edge of Write. The data is written to the RAM at the write
pointer. On the rising edge of
W
, the write pointer is
incremented. Write operations can occur simultaneously or
asynchronously with read operations.
*Including jig and scope capacitances
Figure A. Ouput Load
1.1K
30pF*
680
5V
D.U.T.
2751 drw 03
2751 drw 04
W
RS
AEF, EF
HF, FF
t
RSC
t
RS
t
RSS
t
RSR
t
RSF1
t
RSF2
t
RSS
t
RSR
t
RSQH
t
RSQL
SOCP
Q
4
, Q
6
, Q
7
, Q
8
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| IDT7216L55GB | 制造商:Integrated Device Technology Inc 功能描述: |
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| IDT72200L10TP | 功能描述:IC FIFO 200KB SYNC 10NS 28DIP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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