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參數資料
| 型號： | IDT72132L50P |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Silver Mica Capacitor; Capacitance:910pF; Capacitance Tolerance:+/- 5%; Series:CDS; Voltage Rating:100VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:5.9mm; Leaded Process Compatible:No RoHS Compliant: No |
| 中文描述： | 2K X 9 OTHER FIFO, 50 ns, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數： | 8/13頁 |
| 文件大?。?/td> | 137K |
| 代理商： | IDT72132L50P |
5.36
8
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
NOTE:
1.
EF
,
AEF
,
HF
and
FF
may change status during Retransmit, but flags will be valid at t
RTC
.
Figure 10. Retransmit
Figure 9. Half Full, Almost Full and Almost Empty Timings
2752 drw 11
SICP
t
RFF
0
1
n – 1
R
FF
t
SICFF
t
RFFSI
DATA
OUT
(1)
t
SIS
t
A
SI
Figure 8. Full Boundry Condition Timing
2752 drw 12
SICP
R
HF
t
SICF
7/8 FULL
ALMOST-EMPTY
(1/8 FULL-1)
1/8 FULL
ALMOST FULL (7/8 + 1)
t
RF
7/8 FULL
ALMOST-EMPTY
(1/8 FULL-1)
0
1
n – 2
n – 1
t
SICF
t
RF
AEF
AEF
HALF-FULL
HALF_FULL + 1
HALF-FULL
2752 drw 13
R
SICP
RT
EF
,
AEF
,
HF
,
FF
t
RTC
t
RT
t
RTS
t
RTR
t
RTS
FLAG VALID
0
1
NOTE:
1. After
FF
goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until
FF
goes HIGH.
相關PDF資料 |
PDF描述 |
|---|---|
| IDT72142L50P | Silver Mica Capacitor; Capacitance:100pF; Capacitance Tolerance:+/- 5%; Series:CDV16; Voltage Rating:1000VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:5.94mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
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| IDT7216L55CB | 16 x 16 PARALLEL CMOS MULTIPLIERS |
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| IDT72200L10TP | 功能描述:IC FIFO 200KB SYNC 10NS 28DIP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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