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參數(shù)資料
| 型號： | IDT72132L50P |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Silver Mica Capacitor; Capacitance:910pF; Capacitance Tolerance:+/- 5%; Series:CDS; Voltage Rating:100VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:5.9mm; Leaded Process Compatible:No RoHS Compliant: No |
| 中文描述： | 2K X 9 OTHER FIFO, 50 ns, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大小： | 137K |
| 代理商： | IDT72132L50P |
5.36
2
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Symbol
SI
Serial Input
Name
I/O
I
Description
Serial data is shifted in least significant bit first. In the serial cascade mode, the Serial Input
(SI) pins are tied together and SIX plus D
7
, D
8
determine which device stores the data.
When
RS
is set LOW, internal READ and WRITE pointers are set to the first location of the
RAM array.
HF
and
FF
go HIGH, and
AEF
, and
EF
go LOW. A reset is required before an initial
WRITE after power-up.
R
must be HIGH during an
RS
cycle.
To program the Serial In word width , connect
NW
with one of the Data Set pins (D
7
, D
8
).
Serial data is read into the serial input register on the rising edge of SICP. In both Depth and
Serial Word Width Expansion modes, all of the SICP pins are tied together.
When READ is LOW, data can be read from the RAM array sequentially, independent of SICP.
In order for READ to be active,
EF
must be HIGH. When the FIFO is empty (
EF
-LOW), the
internal READ operation is blocked and Q
0
-Q
8
are in a high impedance condition.
This is a dual-purpose input. In the single device configuration (
XI
grounded), activating
retransmit (
FL
/
RT
-LOW) will set the internal READ pointer to the first location. There is no
effect on the WRITE pointer.
R
must be HIGH and SICP must be LOW before setting
FL
/
RT
LOW. Retransmit is not possible in depth expansion. In the depth expansion configuration,
FL
/
RT
grounded indicates the first activated device.
In the single device configuration,
XI
is grounded. In depth expansion or daisy chain
expansion,
XI
is connected to
XO
(expansion out) of the previous device.
In the Expansion mode, the SIX pin of the least significant device is tied HIGH. The SIX pin
of all other devices is connected to the D
7
or D
8
pin of the previous device. For single device
operation, SIX is tied HIGH.
When
OE
is set LOW, the parallel output buffers receive data from the RAM array. When
OE
is set HIGH, parallel three state buffers inhibit data flow.
Data outputs for 9-bit wide data.
When
FF
goes LOW, the device is full and data must not be clocked by SICP. When
FF
is
HIGH, the device is not full. See the diagram on page 7 for more details.
When
EF
goes LOW, the device is empty and further READ operations are inhibited. When
EF
is HIGH, the device is not empty.
When
AEF
is LOW, the device is empty to 1/8 full or 7/8 to completely full. When
AEF
is HIGH,
the device is greater than 1/8 full, but less than 7/8 full.
This is a dual-purpose output. In the single device configuration (
XI
grounded), the device is
more than half full when
HF
is LOW. In the depth expansion configuration (
XO
connected to
XI
of the next device), a pulse is sent from
XO
to
XI
when the last location in the RAM array
is filled.
The appropriate Data Set pin (D
7
, D
8
) is connected to
NW
to program the Serial In data word
width. For example: D
7
-
NW
programs a 8-bit word width, D
8
-
NW
programs a 9-bit word
width, etc.
Single Power Supply of 5V.
Three grounds at 0V.
RS
Reset
I
NW
SICP
Next Write
Serial Input Clock
I
I
R
Read
I
FL
/
RT
First Load/
Retransmit
I
XI
Expansion In
I
SIX
Serial Input
Expansion
I
OE
Output Enable
I
Q
0
–Q
8
FF
Output Data
Full Flag
O
O
EF
Empty Flag
O
AEF
Almost-Empty/
Almost-Full Flag
O
XO
/
HF
Expansion Out/
Half-Full Flag
O
D
7
, D
8
Data Set
O
V
CC
GND
Power Supply
Ground
2752 tbl 01
STATUS FLAGS
Number of Words in FIFO
IDT72132
0
1-255
256-1024
1025-1792
1793-2047
2048
IDT72142
0
1-511
512-2048
2049-3584
3585-4095
4096
FF
H
H
H
H
H
L
AEF
L
L
H
H
L
L
HF
H
H
H
L
L
L
EF
L
H
H
H
H
H
2752 tbl 02
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72142L50P | Silver Mica Capacitor; Capacitance:100pF; Capacitance Tolerance:+/- 5%; Series:CDV16; Voltage Rating:1000VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:5.94mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
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| IDT7216L55F | 16 x 16 PARALLEL CMOS MULTIPLIERS |
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| IDT7216L55GB | 制造商:Integrated Device Technology Inc 功能描述: |
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| IDT72200L10TP | 功能描述:IC FIFO 200KB SYNC 10NS 28DIP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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