- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377342 > IDT71V3559S85BQ (INTEGRATED DEVICE TECHNOLOGY INC) 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs PDF資料下載
參數(shù)資料
| 型號： | IDT71V3559S85BQ |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs |
| 中文描述： | 256K X 18 ZBT SRAM, 8.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, FBGA-165 |
| 文件頁數(shù)： | 2/28頁 |
| 文件大小： | 996K |
| 代理商： | IDT71V3559S85BQ |
第1頁當前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Pin Definitions
(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol
Pin Function
I/O
Active
Description
A
0
-A
17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/
LD
low
CEN
low and true chip enables.
ADV/
LD
Advance / Load
I
N/A
ADV/
LD
is a synchronous input that is used to load the internal registers wth new address and control when it
is sampled low at the rising edge of clock wth the chip selected. When ADV/
LD
is lowwith the chip
deselected, any burst in progress is termnated. When ADV/
LD
is sampled high then the internal burst
counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/
LD
is
sampled high.
R/
W
Read / Write
I
N/A
R/
W
signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write
access to the memory array. The data bus activity for the current cycle takes place one clock cycle later
CEN
Clock Enable
I
LOW
Synchronous Clock Enable Input. When
CEN
is sampled high, all other synchronous inputs, including clock
are ignored and outputs remain unchanged. The effect of
CEN
sampled high on the device outputs is as if
the low to high clock transition did not occur For normal operation,
CEN
must be sampled lowat rising edge
of clock.
BW
1
-
BW
4
Individual Byte
Write Enables
I
LOW
Synchronous byte write enables. Each 9-bit byte has its own active lowbyte write enable. On load write
cycles (When R/
W
and ADV/
LD
are sampled low) the appropriate byte write signal (
BW
1
-
BW
4
) must be valid.
The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when
R/
W
is sampled high. The appropriate byte(s) of data are written into the device one cycle later
BW
1
-
BW
4
can all be tied lowif always doing write to the entire 36-bit word.
CE
1
,
CE
2
Chip Enables
I
LOW
Synchronous active low chip enable.
CE
1
and
CE
2
are used wth CE
2
to enable the IDT71V3557/59. (
CE
1
or
CE
2
sampled high or CE
2
sampled low) and ADV/
LD
lowat the rising edge of clock, initiates a deselect
cycle. The ZBT
TM
has a one cycle deselect, i.e., the data bus wll tri-state one clock cycle after deselect is
initiated.
CE
2
Chip Enable
I
HIGH
Synchronous active high chip enable. CE
2
is used wth
CE
1
and
CE
2
to enable the chip. CE
2
has inverted
polarity but otherwse identical to
CE
1
and
CE
2
.
CLK
Clock
I
N/A
This is the clock input to the IDT71V3557/59. Except for
OE
, all timng references for the device are made
wth respect to the rising edge of CLK.
I/O
0
-I/O
31
I/O
P1
-I/O
P4
Data Input/Output
I/O
N/A
Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The data
output path is flow-through (no output register).
LBO
Linear Burst Order
I
LOW
Burst order selection input. When
LBO
is high the Interleaved burst sequence is selected. When
LBO
is low
the Linear burst sequence is selected.
LBO
is a static input and it must not change during device operation..
OE
Output Enable
I
LOW
Asynchronous output enable.
OE
must be low to read data fromthe 71V3557/59. When
OE
is HIGH the I/O
pins are in a high-impedance state.
OE
does not need to be actively controlled for read and write cycles. In
normal operation,
OE
can be tied low
TMS
Test Mode Select
I
N/A
Gives input command for TAP controller Sampled on rising edge of TDK. This pin has an internal pullup.
TDI
Test Data Input
I
N/A
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
TCK
Test Clock
I
N/A
Clock input of TAP controller Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven fromthe falling edge of TCK. This pin has an internal pullup.
TDO
Test Data Output
O
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller
TRST
JTAG Reset
(Optional)
I
LOW
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used
TRST
can
be left floating. This pin has an internal pullup.
ZZ
Sleep Mode
I
HIGH
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3557/3559 to
its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal
pulldown.
V
DD
Power Supply
N/A
N/A
3.3V core power supply.
V
DDQ
Power Supply
N/A
N/A
3.3V I/O Supply.
V
SS
Ground
N/A
N/A
Ground.
5282 tbl 02
相關PDF資料 |
PDF描述 |
|---|---|
| IDT71V3559S85BQI | 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs |
| IDT71V3559S85PF | 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs |
| IDT71V3559S85PFI | 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs |
| IDT71V3559SA | 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs |
| IDT71V3559SA75BQI | Ceramic Conformally Coated / Radial 'Standard & High Voltage Golden Max'; Capacitance [nom]: 82pF; Working Voltage (Vdc)[max]: 500V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic, Conformally Coated; Temperature Coefficient: C0G (NP0); Lead Style: Radial Leaded; Lead Dimensions: 0.200" Lead Spacing; Body Dimensions: 0.300" x 0.390" x 0.200"; Container: Bag; Qty per Container: 250 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT71V3559S85BQG | 功能描述:IC SRAM 4MBIT 85NS 165FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應商設備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT71V3559S85BQG8 | 功能描述:IC SRAM 4MBIT 85NS 165FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應商設備封裝:100-TQFP（14x20） 包裝:托盤 |
| IDT71V3559S85BQI | 功能描述:IC SRAM 4MBIT 85NS 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應商設備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT71V3559S85PF | 功能描述:IC SRAM 4MBIT 85NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040 |
| IDT71V3559S85PF8 | 功能描述:IC SRAM 4MBIT 85NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040 |
發(fā)布緊急采購，3分鐘左右您將得到回復。