參數(shù)資料
型號(hào): IDT71V3557S75BG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs
中文描述: 128K X 36 ZBT SRAM, 7.5 ns, PBGA119
封裝: 14 X 22 MM, PLASTIC, BGA-119
文件頁(yè)數(shù): 14/28頁(yè)
文件大?。?/td> 996K
代理商: IDT71V3557S75BG
6.42
14
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used
(1)
CEN
BW
x
Write Operation with Chip Enable Used
(1)
NOTES:
1. H = High; L = Low; X = Dont Care; = Don't Know; Z = High Impedance.
2.
CE
2
timng transition is identical to
CE
1
signal. CE
2
timng transition is identical but inverted to the
CE
1
and
CE
2
signals.
3. Device outputs are ensured to be in High-Z during device power-up.
NOTES:
1. H = High; L = Low; X = Dont Care; = Don't Know; Z = High Impedance.
2.
CE
= L is defined as
CE
1
= L,
CE
2
= L and CE2 = H.
CE
= H is defined as
CE
1
= H,
CE
2
= H or CE
2
= L.
Cycle
Address
R/
W
ADV/
LD
CE
1
(2)
OE
I/O
(3)
Comments
n
X
X
L
H
L
X
X
Deselected.
n+1
X
X
L
H
L
X
X
Z
Deselected.
n+2
A
0
H
L
L
L
X
X
Z
Address A
0
and Control meet setup.
n+3
X
X
L
H
L
X
L
Q
0
Address A
0
read out, Deselected.
n+4
A
1
H
L
L
L
X
X
Z
Address A
1
and Control meet setup.
n+5
X
X
L
H
L
X
L
Q
1
Address A
1
read out, Deselected.
n+6
X
X
L
H
L
X
X
Z
Deselected.
n+7
A
2
H
L
L
L
X
X
Z
Address A
2
and Control meet setup.
n+8
X
X
L
H
L
X
L
Q
2
Address A
2
read out, Deselected.
n+9
X
X
L
H
L
X
X
Z
Deselected.
5282 tbl 19
Cycle
Address
R/
W
ADV/
LD
CE
(2)
CEN
BW
x
OE
I/O
Comments
n
X
X
L
H
L
X
X
Deselected.
n+1
X
X
L
H
L
X
X
Z
Deselected.
n+2
A
0
L
L
L
L
L
X
Z
Address A
0
and Control meet setup
n+3
X
X
L
H
L
X
X
D
0
Data D
0
Write In, Deselected.
n+4
A
1
L
L
L
L
L
X
Z
Address A
1
and Control meet setup
n+5
X
X
L
H
L
X
X
D
1
Data D
1
Write In, Deselected.
n+6
X
X
L
H
L
X
X
Z
Deselected.
n+7
A
2
L
L
L
L
L
X
Z
Address A
2
and Control meet setup
n+8
X
X
L
H
L
X
X
D
2
Data D
2
Write In, Deselected.
n+9
X
X
L
H
L
X
X
Z
Deselected.
5282 tbl 20
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IDT71V3557S75BGI 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs
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