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參數(shù)資料
| 型號： | IDT71P74204S333BQ |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 18Mb Pipelined QDR II SRAM Burst of 4 |
| 中文描述： | 2M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1 MM PITCH, FBGA-165 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大?。?/td> | 592K |
| 代理商： | IDT71P74204S333BQ |
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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information
18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range
Symbol
Pin Function
Description
D[X:0]
Input Synchronous
Data input signals, sampled on the rising edge of K and
K
clocks during valid write operations
2M x 8 -- D[7:0]
2M x 9 -- D[8:0]
1M x 18 -- D[17:0]
512K x 36 -- D[35:0]
BW
0
,
BW
1
BW
2
,
BW
3
Input Synchronous
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of
K
clocks during write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data.
Deselecting a Byte Write Select wll cause the corresponding byte of data to be ignored and not written in to the device.
2M x 9 --
BW
0
controls D[8:0]
1M x 18 --
BW
0
controls D[8:0] and
BW
1
controls D[17:9]
512K x 36 --
BW
0
controls D[8:0],
BW
1
controls D[17:9],
BW
2
controls D[26:18] and
BW
3
controls D[35:27]
NW
0,
NW
1
Input Synchronous
Nbble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects. Sampled on the
rising edge of the K and
K
clocks during write operations. Used to select which nibble is written into the device during the
current portion of the write operations. Nbbles not written remain unaltered. All the nibble writes are sampled on the same
edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not
written in to the device.
SA
Input Synchronous
Address inputs are sampled on the rising edge of K clock during active read or write operations. These address inputs are
multiplexed so a read and write can be initiated on alternate clock cycles. These inputs are ignored when the appropriate
port is deselected.
Q[X:0]
Output Synchronous
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is drven out on the rising
edge of boththe C and
C
clocks during Read operations or K and
K
when operating insingle clock mode. Whenthe Read
port is deselected, Q[X:0] are automatically three-stated.
W
Input Synchronous
Write Control Logic active Low Sampled on the rsing edge ofthe positive input clock (K). When asserted active, a write
operation in intiated. Deasserting wll deselectthe Write port, causing D[X:0] to be ignored. Ifa wrte operation has
successfully been intiated, it wll continue to completion, ignoring the
W
on the followng clock cycle. This allows the user to
continuously hold
W
lowwhile bursting data into the SRAM
R
Input Synchronous
Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a read operation is
initiated. Deasserting wll cause the Read port to be deselected. When deselected, the pending access is allowed to
complete and the output drivers are automatically three-stated followng the next rising edge of the C clock. Each read
access consists of a burst of four sequential transfer If a read operation has successfully been initiated, it wll continue to
completion, ignoring the
R
on the followng clock cycle. This allows the user to continuously hold
R
lowwhile bursting data
fromthe SRAM.
C
Input Clock
Positive Output Clock Input. C is used in conjunction with
C
to clock out the Read data fromthe device. C and
C
can be
used together to deskewthe flight times of various devices on the board back to the controller See application example
for further details.
C
Input Clock
Negative Output Clock Input.
C
is used in conjunction wth C to clock out the Read data fromthe device. C and
C
can be
used together to deskewthe flight times of various devices on the board back to the controller See application example
for further details.
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data
through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
K
Input Clock
Negative Input Clock Input.
K
is used to capture synchronous inputs being presented to the device and to drive out data
through Q[X:0] when in single clock mode.
CQ,
CQ
Output Clock
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs
and can be used as a data valid indication. These signals are free running and do not stop when the output data is three-
stated.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the systemdata bus impedance. Q[X:0]
output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can
be connected directly to V
DDQ,
which enables the mnimumimpedance mode. This pin cannot be connected directly to
GND or left unconnected.
6111 tbl 02a
Pin Definitions
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| IDT71P74604S167BQ | 功能描述:IC SRAM 18MBIT 167MHZ 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
| IDT71P74604S167BQ8 | 功能描述:IC SRAM 18MBIT 167MHZ 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
| IDT71P74604S167BQG | 功能描述:IC SRAM 18MBIT 167MHZ 165FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
| IDT71P74604S167BQG8 | 功能描述:IC SRAM 18MBIT 167MHZ 165FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
| IDT71P74604S200BQ | 功能描述:IC SRAM 18MBIT 200MHZ 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
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