參數(shù)資料
型號: IDT71342LA25J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE
中文描述: 4K X 8 DUAL-PORT SRAM, 25 ns, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 9/13頁
文件大小: 144K
代理商: IDT71342LA25J
6.05
9
IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE
(1)
NOTES:
1.
CE
= V
IH
for the duration of the above timing (both write and read cycle).
2. "DATA
OUT
VALID" represents all I/O's (I/O
0
-I/O
7
) equal to the semaphore value.
NOTES:
1. D
0R
= D
0L
= V
IL
,
CE
R
=
CE
L
= V
IH
, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
3. This parameter is measured from the point where R/
W
"
A
" or
SEM
"
A
" goes High until R/
W
"
B
" or
SEM
"
B
" goes High.
4. If t
SPS
is not satisfied, there is no guarantee which side will be granted the semaphore flag.
A
0"A"
- A
2"A"
t
SPS
R/
W
"A"
SEM
"A"
"A"
SIDE
(2)
A
0"B"
- A
2"B"
R/
W
"
B
"
SEM
"B"
"B"
SIDE
MATCH
MATCH
2721 drw 13
(2)
TIMING WAVEFORM OF SEMAPHORE CONTENTION
(1, 3, 4)
A
0
- A
2
VALID ADDRESS
VALID ADDRESS
DATA
IN
VALID
DATA
OUT
VALID
SEM
R/
W
OE
DATA
0
t
AW
t
EW
t
WR
t
DW
t
DH
t
WP
t
AS
t
SWRD
t
SOP
t
AOE
t
ACE
t
SAA
t
OH
Test Cycle
(Read Cycle)
Write Cycle
2721 drw 12
(2)
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