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參數(shù)資料
| 型號： | IDT71342LA25J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE |
| 中文描述： | 4K X 8 DUAL-PORT SRAM, 25 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大小： | 144K |
| 代理商： | IDT71342LA25J |
IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGE
6.05
8
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/
W
CONTROLLED TIMING
(1, 5, 8)
TIMING WAVEFORM OF WRITE CYCLE NO. 2,
CE
CONTROLLED TIMING
(1, 5)
NOTES:
1. R/
W
or
CE
must be High during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of either
CE
or
SEM
= V
IL
and R/
W
= V
IL
.
3. t
WR
is measured from the earlier of
CE
or R/
W
going High to the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the
CE
Low transition occurs simultaneously with or after the R/
W
Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (
CE
or R/
W
) is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 500mV from steady state with the Output
Test Load (Figure 2).
8. If
OE
is Low during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off data to
be placed on the bus for the required t
DW
. If
OE
is High during an R/
W
controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified t
WP
.
9. To access RAM,
CE
=V
IL
and
SEM
= V
IH
. To access semaphore,
CE
= V
IH
and
SEM
= V
IL
.
Either condition must be valid for the entire t
EW
time.
2721 drw 11
R/
W
t
WC
ADDRESS
DATA
IN
CE
or
SEM
t
DW
t
WR
t
DH
t
EW
t
AS
t
AW
(9)
(6)
(2)
(3)
CE
or
SEM
2721 drw 10
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
R/
W
t
WP
t
DH
DATA
OUT
t
WZ
(4)
(4)
t
OW
OE
t
HZ
t
LZ
t
HZ
(9)
(6)
(7)
(2)
(3)
(7)
(7)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT71342LA25J8 | 功能描述:IC SRAM 32KBIT 25NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應商設備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT71342LA25JGI | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 25NS 52PLCC |
| IDT71342LA25JGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 25NS 52PLCC |
| IDT71342LA25JI | 功能描述:IC SRAM 32KBIT 25NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應商設備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT71342LA25JI8 | 功能描述:IC SRAM 32KBIT 25NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應商設備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
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