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| 型號： | IDT71321LA45TF |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | SILICONE COATED MIL GRADE WIREWOUND RESISTOR AXIAL LEAD, 1 OHM, 0.1%, 50PPM, ROHS |
| 中文描述： | 高速2K × 8雙端口靜態(tài)RAM的中斷 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 255K |
| 代理商： | IDT71321LA45TF |
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range
(5,6)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization
but is not production tested.
2. PLCC package only.
3. For Master/Slave combination, t
WC
= t
BAA
+ t
WP
, since R/W =
V
IL
must occur after t
BAA
.
4.
If
OE
is LOW during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off data to be placed on the
bus for the required t
DW
. If
OE
is High during a R/
W
controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
WP
.
5. 'X' in part numbers indicates power rating (SA or LA).
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Symbol
Parameter
7132X20
(2)
7142X20
(2)
Com'l Only
7132X25
(2)
7142X25
(2)
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
Unit
Min.
Max.
Min.
Max.
Min.
Max.
WRITE CYCLE
t
WC
Write Cycle Time
(3)
20
____
25
____
35
____
ns
t
EW
Chip Enable to End-of-Write
15
____
20
____
30
____
ns
t
AW
Address Valid to End-of-Write
15
____
20
____
30
____
ns
t
AS
Address Set-up Time
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
(4)
15
____
15
____
25
____
ns
t
WR
Write Recovery Time
0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write
10
____
12
____
15
____
ns
t
HZ
Output High-Z Time
(1)
____
10
____
10
____
15
ns
t
DH
Data Hold Time
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1)
____
10
____
10
____
15
ns
t
OW
Output Active from End-of-Write
(1)
0
____
0
____
0
____
ns
2692 tbl 09
Symbol
Parameter
7132X55
7142X55
Com'l &
Military
7132X100
7142X100
Com'l &
Military
Unit
Min.
Max.
Min.
Max.
WRITE CYCLE
t
WC
Write Cycle Time
(3)
55
____
100
____
ns
t
EW
Chip Enable to End-of-Write
40
____
90
____
ns
t
AW
Address Valid to End-of-Write
40
____
90
____
ns
t
AS
Address Set-up Time
0
____
0
____
ns
t
WP
Write Pulse Width
(4)
30
____
55
____
ns
t
WR
Write Recovery Time
0
____
0
____
ns
t
DW
Data Valid to End-of-Write
20
____
40
____
ns
t
HZ
Output High-Z Time
(1)
____
25
____
40
ns
t
DH
Data Hold Time
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1)
____
30
____
40
ns
t
OW
Output Active from End-of-Write
(1)
0
____
0
____
ns
2692 tbl 10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT71421LA45TF | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS |
| IDT7132LA100C | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS |
| IDT7132LA100CB | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS |
| IDT7142LA100CB | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS |
| IDT7132LA100CI | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS |
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| IDT71321LA55PFG8 | 制造商:Integrated Device Technology Inc 功能描述: |
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