參數(shù)資料
型號: IDT7130SA35JGB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
中文描述: 1K X 8 DUAL-PORT SRAM, 35 ns, PQCC52
封裝: 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52
文件頁數(shù): 13/19頁
文件大?。?/td> 167K
代理商: IDT7130SA35JGB
13
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and
BUSY
(2,3,4)
NOTES:
1. To ensure that the earlier of the two ports wins.
t
BDD
is ignored for slave (IDT7140).
2.
CE
L
=
CE
R
= V
IL
3.
OE
= V
IL
for the reading port.
4. All timng is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite fromport "A".
Timing Waveform of Write with
BUSY
(3)
NOTES:
1. t
WH
must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master).
2.
BUSY
is asserted on port "B" blocking R/
W
"B"
, until
BUSY
"B"
goes HIGH.
3. All timng is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite fromport "A".
BUSY
"B"
2689 drw 13
R/
W
"A"
t
WP
t
WH
t
WB
R/
W
"B"
(2)
(1)
,
t
WC
t
WP
t
DW
t
DH
t
BDD
t
DDD
t
BDA
t
WDD
ADDR
"B"
DATA
OUT"B"
DATA
IN"A"
ADDR
"A"
MATCH
VALID
MATCH
VALID
R
W
"A"
BUSY
"B"
t
APS
(1)
2689 drw 12
t
BAA
相關(guān)PDF資料
PDF描述
IDT7130SA35JGI HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
IDT7130SA35L48G HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
IDT7130SA35L48GB HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
IDT7130SA35L48GI HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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