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參數(shù)資料
| 型號(hào)： | IDT70V7319S200DD |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| 中文描述： | 256K X 18 DUAL-PORT SRAM, 10 ns, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大小： | 621K |
| 代理商： | IDT70V7319S200DD |
6.42
IDT70V7319S
High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control
(1,2,3,4)
Upper Byte
I/O
9-17
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS
,
CNTEN
,
REPEAT
are set as appropriate for address access. Refer to Truth Table II for details.
3.
OE
is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
OE
3
CLK
CE
0
CE
1
UB
LB
R/
W
Lower Byte
I/O
0-8
MODE
X
↑
H
X
X
X
X
High-Z
High-Z
Deselected–Power Down
X
↑
X
L
X
X
X
High-Z
High-Z
Deselected–Power Down
X
↑
L
H
H
H
X
High-Z
High-Z
All Bytes Deselected
X
↑
L
H
H
L
L
High-Z
D
IN
Write to Lower Byte Only
X
↑
L
H
L
H
L
D
IN
High-Z
Write to Upper Byte Only
X
↑
L
H
L
L
L
D
IN
D
IN
Write to both Bytes
L
↑
L
H
H
L
H
High-Z
D
OUT
Read Lower Byte Only
L
↑
L
H
L
H
H
D
OUT
High-Z
Read UpperByte Only
L
↑
L
H
L
L
H
D
OUT
D
OUT
Read both Bytes
H
X
X
X
X
X
X
High-Z
High-Z
Outputs Disabled
5629 tbl 02
Truth Table II—Address and Address Counter Control
(1,2,7)
Previous
Address
Used
CLK
ADS
CNTEN
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/
W
,
CE
0
, CE
1
,
UB
/
LB
and
OE
.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4.
ADS
and
REPEAT
are independent of all other memory control signals including
CE
0
, CE
1
and
UB
/
LB
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other memory control signals including
CE
0
, CE
1
,
UB
/
LB
.
6. When
REPEAT
is asserted, the counter will reset to the last valid address loaded via
ADS
. This value is not set at power-up: a known location should be loaded
via
ADS
during initialization if desired. Any subsequent
ADS
access during operations will update the
REPEAT
address location.
7. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address
FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer
to Timng Waveformof Counter Repeat, page 18. Care should be taken during operation to avoid having both counters point to the same bank (i.e., ensure BA
0L
- BA
5L
≠
BA
0R
- BA
5R
), as this condition will invalidate the access for both ports. Please refer to the functional description on page 19 for details.
Address
Addr
REPEAT
(6)
I/O
(3)
MODE
An
X
An
↑
L
(4)
X
H
D
I/O
(n)
External Address Used
X
An
An + 1
↑
H
L
(5)
H
D
I/O
(n+1)
Counter Enabled—Internal Address generation
X
An + 1
An + 1
↑
H
H
H
D
I/O
(n+1)
External Address Blocked—Counter disabled (An + 1 reused)
X
X
An
↑
X
X
L
(4)
D
I/O
(0)
Counter Set to last valid
ADS
load
5629 tbl 03
相關(guān)PDF資料 |
PDF描述 |
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| IDT70V7339S | HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V7339S133BC | HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V7339S133BCI | HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V7339S133BF | HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V7339S133BFI | HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
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參數(shù)描述 |
|---|---|
| IDT70V7339S133BC | 功能描述:IC SRAM 9MBIT 133MHZ 256BGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
| IDT70V7339S133BC8 | 功能描述:IC SRAM 9MBIT 133MHZ 256BGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
| IDT70V7339S133BCI | 功能描述:IC SRAM 9MBIT 133MHZ 256BGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
| IDT70V7339S133BCI8 | 功能描述:IC SRAM 9MBIT 133MHZ 256BGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
| IDT70V7339S133BF | 功能描述:IC SRAM 9MBIT 133MHZ 208FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
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