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參數資料
| 型號： | IDT70V19L |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 3.3V 128K x 9 DUAL-PORT STATIC RAM |
| 中文描述： | 高速3.3 128K的× 9雙端口靜態(tài)RAM |
| 文件頁數： | 14/17頁 |
| 文件大?。?/td> | 265K |
| 代理商： | IDT70V19L |
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Truth Table V —
Address
BUSY
Arbitration
(4)
Inputs
Outputs
14
Functional Description
The IDT70V19 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V19 has an automatic power down
feature controlled by
CE
. The
CE
0
and CE
1
control the on-chip power
down circuitry that permits the respective port to go into a standby
mode when not selected (
CE
= HIGH). When a port is enabled, access
to the entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (
INT
L
) is asserted when the right port writes to memory location
1FFFE (HEX), where a write is defined as
CE
R
= R/
W
R
= V
IL
per the
Truth Table. The left port clears the interrupt through access of
address location 1FFFE when
CE
L
=
OE
L
= V
IL
, R/
W
is a "don't care".
Likewise, the right port interrupt flag (
INT
R
) is asserted when the left
port writes to memory location 1FFFF (HEX) and to clear the interrupt
flag (
INT
R
), the right port must read the memory location 1FFFF. The
message (9 bits) at 1FFFE or 1FFFF is user-defined since it is an
addressable SRAM location. If the interrupt function is not used,
address locations 1FFFE and 1FFFF are not used as mail boxes, but
as part of the random access memory. Refer to Truth Table IV for the
interrupt operation.
NOTES:
1.
Pins
BUSY
L
and
BUSY
R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave.
BUSY
outputs on the IDT70V19 are push-
pull, not open drain outputs. On slaves the
BUSY
input internally inhibits writes.
"L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and
enable inputs of this port. If t
APS
is not met, either
BUSY
L
or
BUSY
R
= LOW will result.
BUSY
L
and
BUSY
R
outputs can not be LOW simultaneously.
Writes to the left port are internally ignored when
BUSY
L
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSY
R
outputs are driving LOW regardless of actual logic level on the pin.
4. Refer to Truth Table I - Chip Enable.
2.
3.
Truth Table VI — Example of Semaphore Procurement Sequence
(1,2,3)
NOTES:
1.
2. There are eight semaphore flags written to via I/O
0
and read from all I/O's (I/O
0
-I/O
8
). These eight semaphores are addressed by A
0
- A
2
.
3.
CE
= V
IH
,
SEM
= V
IL
to access the semaphores. Refer to Truth Table III - Semaphore Read/Write Control.
This table denotes a sequence of events for only one of the eight semaphores on the IDT70V19.
Function
CE
L
CE
R
A
OL
-A
16L
A
OR
-A
16R
BUSY
L
(1)
BUSY
R
(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit
(3)
4853 tbl 17
Functions
D
0
- D
8
Left
D
0
- D
8
Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
4853 tbl 18
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