參數(shù)資料
型號(hào)： IDT70V15L15PFI
廠商： Integrated Device Technology, Inc.
英文描述： HIGH-SPEED 3.3V 16/8K X 9 DUAL-PORT STATIC RAM
中文描述： 高速3.3 16/8K × 9雙端口靜態(tài)RAM
文件頁(yè)數(shù)： 15/18頁(yè)
文件大小： 167K
代理商： IDT70V15L15PFI
6.42
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
15
E
L
I
M
I
N
A
R
Y
PRELIMINARY
the
BUSY
pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the
BUSY
pin for that port LOW.
The
BUSY
outputs on the IDT70V16/5 RAMin master mode, are
push-pull type outputs and do not require pull up resistors to operate. If
these RAMs are being expanded in depth, then the
BUSY
indication for
the resulting array requires the use of an external AND gate.
-+&083
7,23
When expanding an IDT70V16/5 RAMarray in width while using
BUSY
logic, one master part is used to decide which side of the RAMarray
will receive a
BUSY
indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master use
the
BUSY
signal as a write inhibit signal. Thus on the IDT70V16/5 RAM
the
BUSY
pin is an output if the part is used as a master (M/
S
pin = H), and
the
BUSY
pin is an input if the part used as a slave (M/
S
pin = L) as shown
in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating
BUSY
on one side of the
array and another master indicating
BUSY
on one other side of the array.
This would inhibit the write operations fromone port for part of a word and
inhibit the write operations fromthe other port for the other part of the word.
The
BUSY
arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a
BUSY
flag to be output fromthe master before the actual write
pulse can be initiated with the R/
W
signal. Failure to observe this timng can
result in a glitched internal write inhibit signal and corrupted data in the
slave.
&
The IDT70V16/5 are extremely fast Dual-Port 16/8Kx9 Static RAMs
with an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-Port
RAMto claima privilege over the other processor for functions defined by
the systemdesigner
’
s software. As an example, the semaphore can be
used by one processor to inhibit the other fromaccessing a portion of the
Dual-Port RAMor any other shared resource.
The Dual-Port RAMfeatures a fast access time, and both ports are
The IDT70V16/5 provides two ports with separate control, address
and I/O pins that permt independent access for reads or writes to any
location in memory. The IDT70V16/5 has an automatic power down
feature controlled by
CE
. The
CE
controls on-chip power down circuitry
that permts the respective port to go into a standby mode when not selected
(
CE
HIGH). When a port is enabled, access to the entire memory array
is permtted.
(
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(
INT
L
) is asserted when the right port writes to memory location 3FFE
where a write is defined as the
CE
=
R/
W
=
V
IL
per Truth Table III. The
left port clears the interrupt by an address location 3FFE access when
CE
R
=
OE
R
=V
IL
, R/
W
is a "don't care". Likewise, the right port interrupt flag
(INT
R
) is asserted when the left port writes to memory location 3FFF
(1FFF for IDT70V15) and to clear the interrupt flag (INT
R
), the right port
must access location 3FFF. The message (9 bits) at 3FFE or 3FFF (1FFE
or 1FFF for IDT70V15) is user-defined since it is in an addressable SRAM
location. If the interrupt function is not used, address locations 3FFE and
3FFF (1FFE and 1FFF for IDT70V15) are not used as mail boxes but
are still part of the randomaccess memory. Refer to Truth Table III for the
interrupt operation.
3
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAMis
“
busy
”
.
The
BUSY
pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a
BUSY
indication, the write signal is gated internally
to prevent the write fromproceeding.
The use of
BUSY
logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the
BUSY
outputs together
and use any
BUSY
indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of
BUSY
logic is
not desirable, the
BUSY
logic can be disabled by placing the part in slave
mode with the M/
S
pin. Once in slave mode the
BUSY
pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V16/5 RAMs.
5669 drw 18
MASTER
Dual Port
RAM
BUSY
(L)
BUSY
(R)
CE
MASTER
Dual Port
RAM
BUSY
(L)
BUSY
(R)
CE
SLAVE
Dual Port
RAM
BUSY
(L)
BUSY
(R)
CE
SLAVE
Dual Port
RAM
BUSY
(L)
BUSY
(R)
CE
BUSY
(L)
BUSY
(R)
D
相關(guān)PDF資料
PDF描述
IDT70V15L20J HIGH-SPEED 3.3V 16/8K X 9 DUAL-PORT STATIC RAM
IDT70V15L20JI HIGH-SPEED 3.3V 16/8K X 9 DUAL-PORT STATIC RAM
IDT70V15L20PF HIGH-SPEED 3.3V 16/8K X 9 DUAL-PORT STATIC RAM
IDT70V15L20PFI HIGH-SPEED 3.3V 16/8K X 9 DUAL-PORT STATIC RAM
IDT70V15L25J HIGH-SPEED 3.3V 16/8K X 9 DUAL-PORT STATIC RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT70V15L20PF 功能描述:IC SRAM 72KBIT 20NS 80TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF
IDT70V15L20PF8 功能描述:IC SRAM 72KBIT 20NS 80TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI
IDT70V15L25PF 功能描述:IC SRAM 72KBIT 25NS 80TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF
IDT70V15L25PF8 功能描述:IC SRAM 72KBIT 25NS 80TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI
IDT70V15S15PF 功能描述:IC SRAM 72KBIT 15NS 80TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*