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參數(shù)資料
| 型號(hào)： | IDT70V07S55PFI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 高速3.3 32K的× 8雙端口靜態(tài)RAM |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 174K |
| 代理商： | IDT70V07S55PFI |
9
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/
W
Controlled Timing
(1,5,8)
Timing Waveform of Write Cycle No. 2,
CE
Controlled Timing
(1,5)
NOTES:
1. R/
W
or
CE
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a LOW
CE
and a LOW R/
W
for memory array writing cycle.
3. t
WR
is measured fromthe earlier of
CE
or R/
W
(or
SEM
or R/
W
) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE
or
SEM
LOW transition occurs simultaneously with or after the R/
W
LOW transition, the outputs remain in the High-impedance state.
6. Timng depends on which enable signal is asserted last,
CE
or R/
W
.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV fromsteady state with the Output Test Load
(Figure 2).
8. If
OE
is LOW during R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off and data to be placed on the
bus for the required t
DW
. If
OE
is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
WP
.
9. To access SRAM
CE
= V
IL
and
SEM
= V
IH
. To access semaphore,
CE
= V
IH
and
SEM
= V
IL
. t
EW
must be met for either condition.
R/
W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
CE
or
SEM
(6)
(4)
(4)
(3)
2943 drw 09
(7)
(9)
(7)
t
LZ
,
t
HZ
(7)
2943 drw 10
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/
W
t
AW
t
EW
(3)
(2)
(6)
CE
or
SEM
(9)
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