參數(shù)資料
型號: IDT70V07S55PFI
廠商: Integrated Device Technology, Inc.
英文描述: HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
中文描述: 高速3.3 32K的× 8雙端口靜態(tài)RAM
文件頁數(shù): 12/18頁
文件大?。?/td> 174K
代理商: IDT70V07S55PFI
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Timing Waveform of Write with
BUSY
12
Waveform of
BUSY
Arbitration Controlled by
CE
Timing
(1)
NOTES:
1. All timng is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite fromPort “A”.
2. If t
APS
is not satisfied, the
BUSY
signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted.
Waveform of
BUSY
Arbitration Cycle Controlled by Address Match Timing
(1)
NOTES:
1. t
WH
must be met for both
BUSY
input (SLAVE) and output (MASTER).
2.
BUSY
is asserted on Port "B" blocking R/
W
"B"
, until
BUSY
"B"
goes HIGH.
2943 drw 14
R/
W
"A"
BUSY
"B"
t
WP
t
WB
R/
W
"B"
t
WH
(1)
(2)
2943 drw 15
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
2943 drw 16
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
相關(guān)PDF資料
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IDT70V07L25GI HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
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