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參數(shù)資料
| 型號： | IDT70T9359L9BF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2.5V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM |
| 中文描述： | 8K X 18 DUAL-PORT SRAM, 20 ns, PBGA100 |
| 封裝： | FPBGA-100 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 213K |
| 代理商： | IDT70T9359L9BF |
6.42
IDT70T9359/49L
High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
Preliminary
',.,'/7
The IDT70T9359/49 features dual chip enables (refer to Truth Table
I) in order to facilitate rapid and simple depth expansion with no require-
ments for external logic. Figure 4 illustrates how to control the varioius chip
enables in order to expand two devices in depth.
The IDT70T9359/49 can also be used in applications requiring
expanded width, as indicated in Figure 4. Since the banks are allocated
at the discretion of the user, the external controller can be set up to drive
the input signals for the various devices as required to allow for 36-bit or
wider applications.
5640 drw 18
IDT70T9359/49
CE
0
CE
1
CE
1
CE
0
CE
0
CE
1
A
13
/A
12(1)
CE
1
CE
0
V
DD
V
DD
IDT70T9359/49
IDT70T9359/49
IDT70T9359/49
Control Inputs
Control Inputs
Control Inputs
Control Inputs
CNTRST
CLK
ADS
CNTEN
R/
W
LB
,
UB
OE
Figure 4. Depth and Width Expansion with IDT70T9359/49
The IDT70T9359/49 provides a true synchronous Dual-Port Static
RAMinterface. Registered inputs provide mnimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse is independent of the LOW to HIGH transition of the clock
signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory applications.
CE
0
= V
IL
and CE
1
= V
IH
for one clock cycle will power down the
internal circuitry to reduce static power consumption. Multiple chip enables
allow easier banking of multiple IDT70T9359/49's for depth expansion
configurations. When the Pipelined output mode is enabled, two cycles are
required with
CE
0
= V
IL
and CE
1
= V
IH
to re-activate the outputs.
NOTE:
1. A
13
is for IDT70T9359, A
12
is for IDT70T9349.
相關PDF資料 |
PDF描述 |
|---|---|
| IDT70T9359L9BFI | HIGH-SPEED 2.5V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM |
| IDT70T9359L9PF | HIGH-SPEED 2.5V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM |
| IDT70T9359L9PFI | HIGH-SPEED 2.5V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM |
| IDT70T9349L12BF | HIGH-SPEED 2.5V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM |
| IDT70T9349L12BFI | HIGH-SPEED 2.5V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM |
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