參數資料
型號: IDT70T653MS15BCI
廠商: Integrated Device Technology, Inc.
英文描述: HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
中文描述: 高速2.5V的為512k × 36 3.3 5011 2.5V的接口ASYNCHRONO美國雙端口靜態(tài)RAM
文件頁數: 21/24頁
文件大?。?/td> 309K
代理商: IDT70T653MS15BCI
21
IDT70T653M Preliminary
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Sleep Mode
The IDT70T653M is equipped with an optional sleep or low power
mode on both ports. The sleep mode pin on both ports s active high. During
normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the
port will enter sleep mode where it will meet lowest possible power
conditions. The sleep mode timing diagram shows the modes of operation:
Normal Operation, No Read/Write Allowed and Sleep Mode.
For a period of time prior to sleep mode and after recovering from sleep
mode (t
ZZS
and t
ZZR
), new reads or writes are not allowed. If a write or read
operation occurs during these periods, the memory array may be
corrupted. Validity of data out from the RAM cannot be guaranteed
immediately after ZZ is asserted (prior to being in sleep).
During sleep mode the RAM automatically deselects itself. The RAM
disconnects its internal buffer. All outputs will remain in high-Z state while
in sleep mode. All nputs are allowed to toggle. The RAM will not be selected
and will not perform any reads or writes.
JTAG Timing Specifications
TCK
Device Inputs
(1)
/
TDI/TMS
Device Outputs
(2)
/
TDO
TRST
t
JCD
t
JDC
t
JRST
t
JS
t
JH
t
JCYC
t
JRSR
t
JF
t
JCL
t
JR
t
JCH
5679 drw 24
x
NOTES:
1. Device inputs = All device inputs except TDI, TMS, TCK and
TRST
.
2. Device outputs = All device outputs except TDO.
Array A
Array B
TCK
TMS
TRST
TDIA
TDOA
TDIB
TDOB
5679 drw 23
IDT70T653M
JTAG Configuration
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