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| 型號： | IDT70T3589S-133DRI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| 中文描述： | 高速與3.3V 2.5V的256/128/64K × 36 SYNCHRONOU S雙，端口靜態(tài)RAM或2.5V的接口 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 442K |
| 代理商： | IDT70T3589S-133DRI |
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6.42
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
Waveform of Collision Timing
(1,2)
Both
Ports Writing with Left Port Clock Leading
t
SA
t
HA
(3)
t
COLS
t
COLR
A
3
HA
t
SA
t
t
COLS
t
COLR
5666 drw 20
COL
R
COL
L
(4)
CLK
R
ADDRESS
R
A
0
A
1
A
2
t
OFS
(4)
CLK
L
ADDRESS
L
A
0
A
1
A
2
A
3
t
OFS
NOTES:
1.
CE
0
= V
IL
, CE
1
= V
IH
.
2. For reading port,
OE
is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.
3. Leading Port Output flag might output 3t
CYC
2
+ t
COLS
after Address match.
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Collision Detection Timing
(3,4)
Cycle Time
t
OFS
(ns)
Region 1 (ns)
(1)
Region 2 (ns)
(2)
5ns
0 - 2.8
2.81 - 4.6
6ns
0 - 3.8
3.81 - 5.6
7.5ns
0 - 5.3
5.31 - 7.1
5666 tbl 13
NOTES:
1. Region 1
Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.
2. Region 2
Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.
while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.
3. All the production units are tested to midpoint of each region.
4. These ranges are based on characterization of a typical device.
Left Port
Right Port
Function
CLK
L
R/
W
L
(1)
CE
L
(1)
A
17L
-A
0L
(2)
COL
L
CLK
R
R/
W
R
(1)
CE
R
(1)
A
17R
-A
0R
(2)
COL
R
↑
H
L
MATCH
H
↑
H
L
MATCH
H
Both ports reading. Not a valid collision.
No flag output on either port.
↑
H
L
MATCH
L
↑
L
L
MATCH
H
Left port reading, Right port writing.
Valid collision, flag output on Left port.
↑
L
L
MATCH
H
↑
H
L
MATCH
L
Right port reading, Left port writing.
Valid collision, flag output on Right port.
↑
L
L
MATCH
L
↑
L
L
MATCH
L
Both ports writing. Valid collision. Flag
output on both ports.
5666 tbl 14
Truth Table IV — Collision Detection Flag
NOTES:
1.
CE
0 =
V
IL
and
CE
1 =
V
IH
.
R/
W
and CE
are synchronous with respect to the clock and need valid set-up and hold times.
2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
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| IDT70T3589S166BC | HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
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