參數(shù)資料
型號(hào)： IDT70T3589S-133BCI
廠商： Integrated Device Technology, Inc.
英文描述： HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
中文描述： 高速與3.3V 2.5V的256/128/64K × 36 SYNCHRONOU S雙，端口靜態(tài)RAM或2.5V的接口
文件頁(yè)數(shù)： 15/28頁(yè)
文件大小： 442K
代理商： IDT70T3589S-133BCI
6.42
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read
(1,2,4)
CLK
"A"
R/
W
"A"
ADDRESS
"A"
DATA
IN"A"
CLK
"B"
R/
W
"B"
ADDRESS
"B"
DATA
OUT"B"
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
SW
t
HW
t
SA
t
HA
t
CO
(3)
t
CD2
NO
MATCH
VALID
MNO
MATCH
MATCH
VALID
5666 drw 09
t
DC
NOTES:
1.
CE
0
,
BE
n
, and
ADS
= V
IL
; CE
1
,
CNTEN
, and
REPEAT
= V
IH
.
2.
OE
= V
IL
for Port "B", which is being read from.
OE
= V
IH
for Port "A", which is being written to.
3. If t
CO
< minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
t
CO
+ 2 t
CYC2
+ t
CD2
). If t
CO
> minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be t
CO
+ t
CYC2
+ t
CD2
).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read
(1,2,4)
DATA
IN "A"
CLK
"B"
R/
W
"B"
ADDRESS
"A"
R/
W
"A"
CLK
"A"
ADDRESS
"B"
NO
MATCH
MATCH
NO
MATCH
MATCH
VALID
t
CD1
t
DC
DATA
OUT "B"
5666 drw 10
VALID
VALID
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
HW
t
HA
t
CD1
t
CO
t
DC
t
SA
t
SW
(3)
NOTES:
1.
CE
0
,
BE
n, and
ADS
= V
IL
; CE
1
,
CNTEN
, and
REPEAT
= V
IH
.
2.
OE
= V
IL
for the Right Port, which is being read from.
OE
= V
IH
for the Left Port, which is being written to.
3. If t
CO
< minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
t
CO
+ t
CYC
+ t
CD1
). If t
CO
> minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be t
CO
+ t
CD1
).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
相關(guān)PDF資料
PDF描述
IDT70T3589S133BF HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70T3589S-133BF HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70T3589S133BFI HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70T3589S-133BFI HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70T3589S133DR HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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