參數(shù)資料
型號(hào)： IDT70T3519S200DRI
廠商： Integrated Device Technology, Inc.
英文描述： HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
中文描述： 高速與3.3V 2.5V的256/128/64K × 36 SYNCHRONOU S雙，端口靜態(tài)RAM或2.5V的接口
文件頁(yè)數(shù)： 16/28頁(yè)
文件大?。?/td> 442K
代理商： IDT70T3519S200DRI
6.42
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read
(
OE
= V
IL
)
(2)
R/
W
ADDRESS
An
An +1
An + 2
An + 2
An + 3
An + 4
DATA
IN
Dn + 2
CE
0
CLK
5666 drw 11
Qn
Qn + 3
DATA
OUT
CE
1
BE
n
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
CH2
t
CL2
t
CYC2
READ
NOP
READ
t
SD
t
HD
(3)
(1)
t
SW
t
HW
WRITE
(4)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2.
CE
0
,
BE
n
, and
ADS
= V
IL
; CE
1
,
CNTEN
, and
REPEAT
= V
IH
. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since
ADS
= V
IL
constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/
W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
An + 5
DATA
IN
Dn + 3
Dn + 2
CE
0
CLK
5666 drw 12
DATA
OUT
Qn
Qn + 4
CE
1
BE
n
OE
t
CH2
t
CL2
t
CYC2
t
CKLZ
t
CD2
t
OHZ
t
CD2
t
SD
t
HD
READ
WRITE
READ
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
(3)
(1)
t
SW
t
HW
(4)
Timing Waveform of Pipelined Read-to-Write-to-Read (
OE
Controlled)
(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2.
CE
0
,
BE
n
, and
ADS
= V
IL
; CE
1
,
CNTEN
, and
REPEAT
= V
IH
.
3. Addresses do not have to be accessed sequentially since
ADS
= V
IL
constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
相關(guān)PDF資料
PDF描述
IDT70T3519S-200DRI HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70T3589S133BC HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70T3589S-133BC HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70T3589S133BCI HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70T3589S-133BCI HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
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