參數(shù)資料
型號: IDT709089S12PFI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 64K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM
中文描述: 64K X 8 DUAL-PORT SRAM, 25 ns, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
文件頁數(shù): 8/17頁
文件大?。?/td> 199K
代理商: IDT709089S12PFI
6.42
IDT709089S/L
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Preliminary
$+:)/
@A$%%-
FT
*'
BCB
30
'D
#
"!;#
$+:)/)-
FT
*'
BCB
30
'8
#
"!;#
NOTES:
1. Transition is measured 0mV fromLow or High-impedance voltage with the Output Test Load (Figure 2).
2.
OE
is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3.
ADS
= V
IL
,
CNTEN
and
CNTRST
= V
IH
.
4. The output is disabled (High-Impedance state) by
CE
0
= V
IH
or CE
1
= V
IL
following the next rising edge of clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since
ADS
= V
IL
constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
6. "
X
" denotes Left or Right port. The diagramis with respect to that port.
An
An + 1
An + 2
An + 3
t
CYC1
t
CH1
t
CL1
R/
ADDRESS
DATA
OUT
0
CLK
OE
t
SC
t
HC
t
CD1
t
CKLZ
Qn
Qn + 1
Qn + 2
t
OHZ
t
OLZ
t
OE
t
CKHZ
3242 drw 07
(1)
(1)
(1)
(1)
(2)
CE
1
(4)
t
SW
t
HW
t
SA
t
HA
t
DC
t
DC
(5)
t
SC
t
HC
An
An + 1
An + 2
An + 3
t
CYC2
t
CH2
t
CL2
R/
ADDRESS
0
CLK
CE
1
(4)
DATA
OUT
OE
t
CD2
t
CKLZ
Qn
Qn + 1
Qn + 2
t
OHZ
t
OLZ
t
OE
3242 drw 08
(1)
(1)
(1)
(2)
t
SC
t
HC
t
SW
t
HW
t
SA
t
HA
t
DC
t
SC
t
HC
(5)
(1 Latency)
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