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| 型號(hào)： | IDT70825L25G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | High Speed Low-Noise JFET-Input Dual Operational Amplifier 8-CDIP -55 to 125 |
| 中文描述： | 8K X 16 STANDARD SRAM, 25 ns, CPGA84 |
| 封裝： | PGA-84 |
| 文件頁(yè)數(shù)： | 7/21頁(yè) |
| 文件大?。?/td> | 319K |
| 代理商： | IDT70825L25G |
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IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.31
7
TRUTH TABLE II – SEQUENTIAL READ
(1,2,3,6,8)
Inputs/Outputs
CNTEN
SR/
L
H
L
H
L
MODE
SCLK
SCE
W EOB1
EOB2
SOE
SI/O
L
L
L
L
L
H
H
H
H
H
LOW
LAST
LAST
LAST
LOW
LAST
LAST
LOW
LAST
LOW
L
L
L
L
H
[EOB1]
[EOB1 - 1]
[EOB2]
[EOB2 - 1]
HIGH-Z
Counter Advanced Sequential Read with
EOB
1 reached.
Non-Counter Advanced Sequential Read, without
EOB
1 reached.
Counter Advanced Sequential Read with
EOB
2 reached.
Non-Counter Advanced Sequential Read without
EOB
2 reached.
Counter Advanced Sequential Non-Read with
EOB
1 and
EOB
2
reached.
3016 tbl 11
3016 tbl 12
TRUTH TABLE I – RANDOM ACCESS READ AND WRITE
(1,2)
Inputs/Outputs
CE
CMD
R/
W
OE
LB
UB
I/O
0
-I/O
7
L
H
H
L
L
L
DATA
OUT
L
H
H
L
L
H
DATA
OUT
L
H
H
L
H
L
High-Z
L
H
L
H
(3)
L
L
DATA
IN
L
H
L
H
(3)
L
H
DATA
IN
L
H
L
H
(3)
H
L
High-Z
H
H
X
X
X
X
High-Z
L
H
H
H
X
X
High-Z
L
H
X
X
H
H
High-Z
H
L
L
H
(3)
L
(4)
L
(4)
DATA
IN
H
L
H
L
L
(4)
L
(4)
DATA
OUT
MODE
I/O
8
-I/O
-
DATA
OUT
High-Z
DATA
OUT
DATA
IN
High-Z
DATA
IN
High-Z
High-Z
High-Z
DATA
IN
DATA
OUT
Read both Bytes.
Read lower Byte only.
Read upper Byte only.
Write to both Bytes.
Write to lower Byte only.
Write to upper Byte only.
Both Bytes deselected and powered down.
Outputs disabled but not powered down.
Both Bytes deselected but not powered down.
Write I/O
0
-I/O
12
to the Buffer Command Register.
Read contents of the Buffer Command Register via I/O
0
-I/O
12
.
NOTES:
1. H = V
IH
, L = V
IL
, X = Don't Care, and High-Z = High-impedance.
2.
RST
,
SCE
,
CNTEN
, SR/
W
,
SLD
,
SSTRT
1,
SSTRT
2, SCLK, SI/O
0
-SI/O
15
,
EOB
1,
EOB
2, and
SOE
are unrelated to the random access port control and
operation.
3. If
OE
= V
IL
during write, t
WHZ
must be added to the t
WP
or t
CW
write pulse width to allow the bus to float prior to being driven.
4. Byte operations to control register using
UB
and
LB
separately are also allowed.
TRUTH TABLE III – SEQUENTIAL WRITE
(1,2,3,4,5,6,7,8)
Inputs/Outputs
SCLK
SCE CNTEN
SR/
W EOB1EOB2 SOE
L
H
L
LAST LAST
L
L
L
LOW
H
H
X
LAST LAST
H
L
X
NEXT NEXT
MODE
SI/O
SI/O
IN
Non-Counter Advanced Sequential Write, without
EOB
1 or
EOB
2 reached
SI/O
IN
Counter Advanced Sequential Write with
EOB
1 and
EOB
2 reached.
High-Z No Write or Read due to Sequential port Deselect. No counter advance.
High-Z No Write or Read due to Sequential port Deselect. Conter does advance.
H
H
X
X
LOW
NOTES:
1. H = V
IH
, L = V
IL
, X = Don't Care, and High-Z = High-impedance. LOW = V
OL
.
2.
RST
,
SLD
,
SSTRT
1,
SSTRT
2 are continuously HIGH during a sequential write access, other than pointer access operations.
3.
CE
,
OE
, R/
W
,
CMD
,
LB
,
UB
, and I/O
0
-I/O
15
are unrelated to the sequential port control and operation except for
CMD
which must not be used concurrently
with the sequential port operation (due to the counter and register control).
CMD
should be HIGH (
CMD
= V
IH
) during sequential port access.
4.
SOE
must be HIGH (
SOE
=V
IH
) prior to write conditions only if the previous cycle is a read cycle, since the data being written must be an input at the rising
edge of the clock during the cycle in which SR/
W
= V
IL
.
5. SI/
OIN
refers to SI/O
0
-SI/O
15
inputs.
6. "LAST" refers to the previous value still being output, no change.
7. Termination of a write is done on the Low-to-High transition of SCLK if SR/
W
or
SCE
is High.
8. When
CLKEN
=Low, the address is incremented on the next rising edge before any operation takes place. See the diagrams called "Sequential Counter
Enable Cycle after Reset, Read (and write) Cycle".
3016 tbl 13
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