參數(shù)資料
型號(hào)： IDT70825L25G
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： High Speed Low-Noise JFET-Input Dual Operational Amplifier 8-CDIP -55 to 125
中文描述： 8K X 16 STANDARD SRAM, 25 ns, CPGA84
封裝： PGA-84
文件頁(yè)數(shù)： 11/21頁(yè)
文件大?。?/td> 319K
代理商： IDT70825L25G
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.31
11
RANDOM ACCESS PORT: AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(2,3)
IDT70825X20
Com'l. Only
Min.
IDT70825X25
Com'l. Only
Min.
IDT70825X35
IDT70825X45
Symbol
READ CYCLE
t
RC
t
AA
t
ACE
t
BE
t
OE
t
OH
t
CLZ
t
BLZ
t
OLZ
t
CHZ
t
BHZ
t
OHZ
t
PU
t
PD
Parameter
Max.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
Address Access Time
Chip Enable Access Time
Byte Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Chip Select Low-Z Time
(1)
Byte Enable Low-Z Time
(1)
Output Enable Low-Z Time
(1)
Chip Select High-Z Time
(1)
Byte Enable High-Z Time
(1)
Output Enable High-Z Time
(1)
Chip Select Power-Up Time
Chip Select Power-Down Time
20
—
—
—
—
3
3
3
2
—
—
—
0
—
—
20
20
20
10
—
—
—
—
10
10
9
—
20
25
—
—
—
—
3
3
3
2
—
—
—
0
—
—
25
25
25
10
—
—
—
—
12
12
11
—
25
35
—
—
—
—
3
3
3
2
—
—
—
0
—
—
35
35
35
15
—
—
—
—
15
15
15
—
35
45
—
—
—
—
3
3
3
2
—
—
—
0
—
—
45
45
45
20
—
—
—
—
15
15
15
—
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Transition measured at
±
200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part number indicates power rating (S or L).
3.
CMD
access follows standard timing listed for both read and write accesses, (
CE
= V
IH
when
CMD
= V
IL
) or (
CMD
= V
IH
when
CE
= V
IL
).
RANDOM ACCESS PORT: AC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE
(2,4)
IDT70825X20
Com'l. Only
Min.
IDT70825X25
Com'l. Only
Min.
IDT70825X35
IDT70825X45
Symbol
WRITE CYCLE
t
WC
t
CW
t
AW
t
AS
t
WP
t
BP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Parameter
Max.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle Time
Chip Select to End-of-Write
Address Valid to End-of-Write
(3)
Address Set-up Time
Write Pulse Width
(3)
Byte Enable Pulse Width
(3)
Write Recovery Time
Write Enable Output High-Z Time
(1)
Data Set-up Time
Data Hold Time
Output Active from End-of-Write
20
15
15
0
13
15
0
—
13
0
3
—
—
—
—
—
—
—
10
—
—
—
25
20
20
0
20
20
0
—
15
0
3
—
—
—
—
—
—
—
12
—
—
—
35
25
25
0
25
25
0
—
20
0
3
—
—
—
—
—
—
—
15
—
—
—
45
30
30
0
30
30
0
—
25
0
3
—
—
—
—
—
—
—
15
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Transition measured at
±
200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part number indicates power rating (S or L).
3.
OE
is continuously HIGH,
OE
= V
IH
. If during the R/
W
controlled write cycle the
OE
is LOW, t
WP
must be greater or equal to t
WHZ
+ t
DW
to allow the I/O
drivers to turn off and on the data to be placed on the bus for the required t
DW
. If
OE
is HIGH during the R/
W
controlled write cycle, this requirement does
not apply and the minimum write pulse is the specified t
WP
. For the
CE
controlled write cycle,
OE
may be LOW with no degradation to t
CW
timing.
4.
CMD
access follows standard timing listed for both read and write accesses, (
CE
= V
IH
when
CMD
= V
IL
) or (
CMD
= V
IH
when
CE
= V
IL
).
3016 tbl 21
3016 tbl 20
CASES 8 AND 9: (RESERVED)
Illegal operations. All outputs will be HIGH on the I/O bus during a READ.
相關(guān)PDF資料
PDF描述
IDT70825L25GB High Speed Low-Noise JFET-Input Dual Operational Amplifier 8-CDIP -55 to 125
IDT70825L25PF High Speed Low-Noise JFET-Input Dual Operational Amplifier 20-LCCC -55 to 125
IDT70825L25PFB High Speed Low-Noise JFET-Input Dual Operational Amplifier 8-CDIP -55 to 125
IDT70825S High Speed Low-Noise JFET-Input Dual Operational Amplifier 8-CDIP -55 to 125
IDT70825S20G High Speed Low-Noise JFET-Input Dual Operational Amplifier 10-CFP -55 to 125
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